Beginner device CPLD/FPGA selection for anti-aliasing filter
Hi all, I am working on a HW design for power analysis of 8channel 50/60Hz signals that are sampled @ around 50kHz / channel. These signals needs to be filtered after sampling before transformation in...
View ArticleQuartus II 13.1 with Cyclone V GX Starter Kit
Hi, I am planing to get Cyclone V GX Starter Kit to play with and would like to confirm if the Quartus II 13.1 web edition supports the board. I looked at...
View ArticleNiosII flash programmer/epcs/sdram
Hello guys !! I've seen there are some posts about this topic in the forum but I can't nonetheless program my device.. I've generated a QSYS system with: clock niosII processor sdram controller epcs...
View ArticleSignalTap: Greyed out Options
I'm trying to do some configurations in SignalTap, but alot of options are greyed out, and I can't figure out why. I can add nodes, but I can't remove them. I can change trigger conditions for each...
View ArticleSound on DE2i-150
Hi! Has anyone successfully been able to output sound on their DE2i-150 board? The board's default program and one of the demonstrations that came with the CD are supposed to play audio, however they...
View Article[SystemVerilog] Passing "inout" thru verbatim
Hi all, I have an Altera DE2-115 board and am working on interfacing with the asynchronous static RAM chip. I have gotten a simple test harness working, but only if it is the top-level entity. (See...
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PCIe Gen3 on DE5-net/Stratix V board
Hi All, I've been trying to create a simple design using the Stratix V PCIe 3.0 x8 core with an Avalon-ST interface. I can compile my design, and load it onto the FPGA, but link training fails to...
View ArticleSDR SDRAM controller ref-sdr-sdram-vhdl
Hi all, I am new to VHDL design and I'm trying to the SDRAM controller code found here http://www.altera.com/products/ip/al...sdr_sdram.html. It appears to be incomplete though. When I try to simulate...
View Articleref-sdr-sdram-vhdl controller reference design missing components
Hi all, I am new to VHDL design and I'm trying to the SDRAM controller code found here http://www.altera.com/products/ip/al...sdr_sdram.html. It appears to be incomplete though. When I try to simulate...
View ArticlePCIe full-duplex DMA for Stratix IV
The PCIe reference desgin of StratixIV does not support full-duplex DMA. How to modify the source code of chaining-DMA?
View ArticleIs there an archive for QuartusII Setting Reference Manuals?
Hi Is there an easy way to get access to older QuartusII setting reference manuals? I've looked at the Handbook archive and can't find any. Only the latest one is available on the documentation page...
View ArticleRS 232 demo program for DE2 115 altera kit
Hi all, If any one has worked on RS 232 connector on and got any demo programs.. plz share. needed urgently. Thanking you.... VEER. :confused::confused::confused::confused:
View ArticleTimequest Constraints for Asynchronous RAM and SPI-like Input Devices
I'm new to Timequest. In my designs I use a couple of types of interface that I'm not sure how to write suitable Timequest constraints for and would like some help and examples if possible. The first...
View ArticlevxWorks and Cyclone V SoC HPS->FPGA bridge
Hello, I am very new with vxWorks and Altera. I normally work with QNX and Xilinx. I have tuned a vxworks image. I have test some tasks in RTP and DKM modes. Fron DKM I can read from physical memory...
View ArticleHow to simulate Nios 2 processor based system correctly
Hello everyone, I am working on Network on Chip. I made one system including Nios II Processor, uart, on-chip memory, and my vhdl file in which nios 2 sends and receive the data. For this system i have...
View ArticleArrow SoCkit : generate SD card
Hi everybody, My goal is to instantiate the HPS SDRAM interface to make FPGA and HPS use the same DDR. I have many troubles because the waitrequest of the interface is stack to 1 and so the FPGA can't...
View Article13.1 IP License Issues
All, I am encountering two issues that are preventing me from using licensed IP within Quartus. 1) Whenever I add a license file (.dat) for an IP core, Quartus always "forgets" it whenever I restart...
View ArticleIs SoC EDS web version only good for linux?
Hi all, This is mostly related to SoCkit dev. board although I do not have it yet. I'm trying to figure what the difference between the free and paid version of the SoC EDS are. I saw a table that...
View ArticleNIOS 2 "problem"
BONJOUR Je suis un débutant sur nios2, je n'arrive pas à comprendre, est que quelqu'un peut me guider sur ce sujet : (: (: ( : Cry: merci
View ArticleNIOS II multi core system
hi i am using cyclone II EP2C35F6726C6, i have try to create dual core system but unable to download .elf file. so can you suggest NIOS II IDE software building step
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