counter
I am currently using de1 board and Altera quartus II software. as a beginner to digital design, I am learning by going through the Altera lab exercise. I am stacked on trying to design a 4bit t ff...
View Articlelittle code problem in simulation
Hello everyone, I have a little code problem that I can't resolve. All the signals are green except the "uit" signal. Can anyone see in the code what the problem is ? Thanks Here is the file: library...
View ArticleUnconstrained output ports
Hello sir, I want to place a DDR SDRAM (MT46V64M8 – 16 Meg x 8 x 4 banks) with cyclone IV E (ep4ce55f23i7) device. On doing the Early Pin Planning of DDR with this device I am getting warning of...
View Articlecyclone ii and ddr sdram interfacing
hi, i am using cyclone ii ep2c50 484 pin package, i am interfacing ddr sdram to fpga. here for data fpga has dedicated pins but for address and controls it doesn't have any dedicated pins. can u...
View Article* Warning: Design size of 42 instances exceeds ModelSim ALTERA recommended...
Hi, I have designed a nios system and eclipse program and trying to simulate using modelsim altera starter edition. I am not getting wave properly.The below warning is the ssue???? * Warning: Design...
View ArticleUnable to install the MAX+PLUS 2 baseline10_2.exe file
Hello, I apologize if this has been asked before, but I was not able to find anything in the search. I am trying to install the MAX+PLUS 2 baseline10_2.exe software on my Windows 7 64-bit machine. I am...
View Articlespeech recognition system
Hi everyone, I'm doing a project using cyclone II DE2 altera board. Anyone have done or read about this title? Can teach me how to do the coding part? Thanks you very much castle zone
View ArticleTiming problem
Hello every body; I have a pipelined custom component that have a fixed latency, I made a Nios c code to access this component directly through its base address ,this component work with the same clk...
View ArticleQsys CFI (Common Flash memory Interface) is missing connections
Having a problem with the Qsys CFI memory interface: when a CFI interface is added to a Qsys Nios system, there are very important memory control lines that are not "brought out" of the system,...
View ArticleError after invoking a large number of OpenCL kernels
Hi, I'm currently experiencing an error after invoking a large number of the same OpenCL kernels. The OpenCL kernel itself work fine when run on its own. However I need the host program to launch this...
View ArticleLCD Master interface and NIOS Pipeline issue
I all, I've a SoC based on a NIOSII/f and a LCD controller with a Master interface for accessing the memories in order to update the display content. Here is the function I use to "clear/fill-up with a...
View ArticleBest Development Board to cut my teeth / kick the wheels
Hello, I am wanting to learn more about FPGA development and was just wondering what is a good development kit to start off with to learn about programming FPGAs. I am an engineer and I am mainly...
View ArticleClik here to view.
Timing issue
Hi , i compile my project with Quartus and i have critical error : "Timing requierements not met" and the TimeQuest Timing Analyzer painted red . The clk_in Frequency to the FPGA is 25MHz entered to...
View Articlethe Quotient is floating point in vhdl
hi all if i want to divide two numbers and i know the result would be float . what can i do it and how to specify the output from division thanks a lot.
View ArticleImage Processing on DE2 development board Cyclone II
Greeting! I am very new to image processing. I have a project of image processing using DE2 board and the transmitter is CMOS camera TCM8230MD(A). basically what the project should do is get the image...
View ArticleDE0 CycloneIII development board
So I'm new to the exciting world of FPGAs... For some reason the pin assignments I set up don't actually get to the board via programming. If I set the inputs to the switches and the outputs to the...
View ArticleAltdq_dqs2
Hello Everyone, We are using Arria V GX and the IP ALTDQ_DQS2 with dynamic configuration scan chain. Unfortunately, we cannot complete to compile our design as error occurs. The error messages are as...
View ArticleReal numbers on altera fpga de5
Hi all, The problem that I m facing is that I have to perform some operations that are mostly logarithms exponentials multiplications division and additions on Real numbers. From the simulation point...
View ArticleTimequest Timescale
Are timequest timing constraints always in nanseconds? I have trawled through the documents, the help system, the forum and via Gxxgle, finding nothing. If I put "5ns" in an SDC is the ns ignored?...
View ArticleCompile of GSL
HI, I try to integrate GSL GNU Library into Nios IDE. The encountered problem is in the Linking level: undefined reference to `gsl_sf_bessel_J0' collect2: ld returned 1 exit status. Many person...
View Article