Indefinite states of State Machine - VHDL

Hi Guys,
I would like to ask for your help...

I wrote a simple code that is identifying the rising edge of incoming signal. There are two states - every time that rising edge existing, the state machine moving the other state. In every state there are counter in order to check how many Primary Clock Cycles = 50MHz there are in every cycle of the incoming signal. Every "rise edge" of incoming signal causes to the counter to make reset and moving to another stage.

Simulation in ModelSin is successfull. When I trying to see the code behavior in Signal Tap - Quartus, I see that is works but incorrectly. Sometimes there are state x"00" when there are only two defined states - State_1 and State_2 only!!!

The Fmax of the code is something like 130MHz, I tried to reduce the Primary Clock to the 10MHz value, but it didn't help.

This occures once for sometimes. Independent of frequency of the Incoming signal(1KHz - 1MHz). Looks like when Flip-Flop missing the signal but it's impossible cause the Fmax is higher alot.

Thanks alot...

Y.