ALTREMOTE_UPDATE vs PFL megafunctions
I think I have read too much about Remote Update to completely confuse me. I have a Cyclone IV FPGA that I want to remotely update. I need to find out which Megafunction should I use. Basically if...
View ArticleVerilog code for bram
Hi, I need to implement multi-port memories for stratix series for my thesis work. If anybody could suggest/give sample verilog codes to implement bram it will be of great help to me. I am having...
View Articlecic filter vhdl code
hi..i am student and i am doing a project on software defined radio..it includes a cic filter.as i am new to it i am finding difficulty.pls can any one help me out with a vhdl code for cic filter as...
View ArticleInterfacing Cyclone IV FPGA with Marvell PHY 88E1111 using SGMII
Hi I am using the cyclone IV with SGMII interfaced with Marvell PHY 88E1111. So what are the registers to be configured in the phy and how can I configure it for SGMII.
View ArticleIndefinite states of State Machine - VHDL
Hi Guys, I would like to ask for your help... I wrote a simple code that is identifying the rising edge of incoming signal. There are two states - every time that rising edge existing, the state...
View Articleunable to read data on Interrupt
I have ALtera DE2_115 Board having Cyclone IV E, I am getting 8 bit data on 8-bit bus @ 125 kbps along with Clock. now i treat this clock (125kbps) as a interrupt and read 8-bit bus data on every...
View Articleflash memory integration with Nios II in qsys
hi, I want to implement a system which have nios 2 processor on chip is to communicate with the on board flash(cfi) memory (not a compact flash). i dont know how to integrate with nios2 and axi bus by...
View ArticleFlash memory controller ...
Hi, Where can i found flash memory (common flash) controller IP in altera quartus 2 ... plz help me
View ArticleCan cyclone III comes into the user mode if AP config failed?
I can't find the EP3C120F780I7N when scan the JTAG chain. I want to kown what happend when nSTATUS and CONF_DONE be drived low after power up, and the nCONFIG is high(3.3V)? I have read the datasheet,...
View ArticleHow to initialize external SRAM from Eclipse?
Hi all! I have an embedded system with a Nios processor (with its dedicated on-chip mem) and an external, off-chip 32MB SDRAM (only for data). The system is working fine and I can both read and write...
View ArticleSoftware Guard DB25 plug into laptop USB
I have a Software Guard dongle that plugs into my computers LPT1 printer port. I would like to move the dongle to a laptop, which, of course, does not have an LPT1 port. Could I just use a USB to DB25...
View ArticleTransciever channel placement order for PCIe in stratix V
Is it necessary to have transceiver channel placements in-order to use PCIe Hard IP in stratix V FPGA. For instance, for a 8-lane PCIe hard IP endpoint can I place channels in the following order...
View ArticleOne question about nios2_multiprocessor
tt_nios2_multiprocessor_tutorial provides an example design which builds a multiprocessor system containing three processors that all share a memory buffer.Using the Nios II Integrated Development...
View Articlewhere i can found flash(common) memory ip in qsys
where i can found(flash) memory ip in altera ..... can any one help. i didn't found in qsys ..... with loads of thanx manju540
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ARRIA II GX125 Dev Kit JTAG problem (UNKNOWN ID)
Hi Sir, We are using a Arria II GX 125 dev board from ALTERA. it work well before. But now , it failed in JTAG download. In the Auto detect in programmer, a device named UNKNOWN_C0829037 will be...
View ArticleIn qsys,can PCIe IP receive write request that exceeds 512 bytes?
We design our fpga project based on cyclone iv EP4CGX15 without external ram. Since PCIe IP spec says: "A Qsys-generated PCI Express Avalon-MM bridge accepts Avalon-MM burst write requests with a burst...
View Articleflash(common) memory IP
hi, In the Qsys where i can found flash memory IP core. i searched in Qsys External memory controller's list. I didn't get it .... Can any one help me where i can get Common Flash memory controller IP .
View Articledifference between `include and include
It seems ppl use `include to add file that is required to instantiate component in verilog, but when I use `include in my testbench, a warning is issued after successful compile: ** Warning:...
View ArticleMultiple Nios2 cores inside an FPGA?
Hello, Is it possible to have >1 Nios2 core inside a modern cyclone FPGA? And if so, can all the Altera development tools support this sort of platform? Thanks! Lefty
View ArticleAsynchronous Signal
Hi. I have a problem that my FPGA design failing after several seconds. The code purposes isto measurement frequency from external signal generator (50kHz)*. I'm working with 50Mhz clock, LPM_Divide...
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