How to turn off the optimization that removes repeated logic?

Hi,

I'm creating a small program using a block diagram. I want a propagation delay on a certain signal, so i've put in 2 not gates for this propagation delay. How do i disable the optimization in Quartus to stop it removing these two not gates within a block diagram? I know how to do it in verilog but i need to know how to do it with a block diagram.

I've attempted to go in to the Assignment Editor, selecting the logic elements in the 'To' cell, and choosing 'Netlist Optimazations' in the 'Assignment Name', with a 'Value' of 'Never Allow' and for it to enable this assignment. I've also attempted the same with 'Perform Physical Synthesis for Combinational Logic for Performance' with a 'Value' of 'Off'.
But when i look in the RTL viewer, the not gates have been removed.

Any help is much appreciated.