Cyclone V PLL desired output frequency

Hi! I have a problem using Altera PLL V 12.1 megafunction for Cyclone V.

I choosed integer type of PLL and typed 20 MHz for Reference Clock Frequency.
After that I choosed two output clock, outclk0 and outclk1. In desired outclk0 frequency I typed 50 MHz, and that works fine.
In desired outclk1 frequency I typed 0.2 MHz, because I needed a frequency 200 KHz.
But PLL told me that maximum frequency that it can reach is 1.171875 MHz.
I tried another frequencies, and can tell that 0.6 MHz is last freq that PLL can synthesize correctly.

I also tried fractional PLL. GUI told me that minimum input frequency for fractional PLL is 50 MHz, so I choosed 50 MHz and
also tried to achieve desired outclk1 frequency 0.2 MHz. Another fail, ~0.78 MHz was the frequency which PLL could synthesize.

I worked for a 1 year with Cyclone IV and it's PLL can achieve such requirements without problem.

Can anyone tell me, is it a bug? Or I need to synthesize freqeuncies lower than 0.6 MHz only using VHDL/verilog code (counters), or maybe I can cascade PLL for that reason?
What is a better way of doing it?