Mixing VHDL and Verilog

I have the Terasic Cyclone V board. They generate a Verilog top module with the board signal names that connect to the pins.
I have a VHDL file that instantiates this Verilog top module to get access to the board signals. However, when I program
the board my VHDL doesn't work.

I created a VHDL file with the board signal names and got rid of the Verilog file. That works.

How come my VHDL code did not work when Verilog was the top file with the board signal names?