Maxplus II download required 9.01
Hi, I am looking for a copy of max plus II 9.01 is there any where official I can download it from?
View ArticleQuartus Response Speed
Hi All, I've noticed that when working with Quartus, at times it will slow down its response speed, and saving a file or project can go from nearly instantaneous to take well over 30 seconds....
View ArticleMixing VHDL and Verilog
I have the Terasic Cyclone V board. They generate a Verilog top module with the board signal names that connect to the pins. I have a VHDL file that instantiates this Verilog top module to get access...
View ArticleTwo processors with onchip memory
Hi, I am developing a project with two processors and I'm just trying to send data from pc to master cpu through uart and then from master send that data to slave cpu and then back to pc though the...
View ArticleCyclone IV Transciever Starter Kit
I am yet to be successful to commit NIOS II software to Flash. I plan to use the "Update Portal" method since that works fine for the FPGA code . I have the following to generate my nios_flash_sw.flash...
View ArticleFailed to read UART with non blocking mode
Hi I am working with Altera FPGA DE2 with with Nios II 13.0sp1 Software Build Tools for Eclipse, first I worked with UART with blocking mode using open(), read() and write() functions, It worked fine,...
View ArticleBaremetal?!!
By way of democracy ask to create forum "Baremetal", then I kill this message ! :)
View ArticleDoes Quartus support using a VHDL configuration as a top-level entity?
The question title says it all. I thought it would be pretty straightforward to do so, since Quartus already handles most of the configuration capabilities of VHDL, and this should be possible as...
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Cyclone V - Counter not counting correctly
Hi, I don't know if this is the correct section for this issue since it could also be a VHDL problem, but because I think my source code is correct, I post it here. My (serious) problem is that I use a...
View Articledifference of nios II\e and nios II\f processor
Hi I am new to NIOS II processor.wants to know the main difference of NIOS II\e and NIOS II\f processor and i wants to update the processor from NIOS II\f to nios II\e. what will be the major changes...
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modelsim testbench problem
Hi, I'm trying to simulate a system. Please find the attachement for the code. Running the RTL simulation, I can't see in Modelsim the "i2c_slave_device" component. Where am I wrong? PS: I wrote the...
View ArticleFPGA code program vhdl
A. I have two 6 bit numbers outputs(image and word comparison) in scale 32 which are the results of my program.How i can show one of the two 6 bit numbers in scale from 100(if this can't be done i can...
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Installing Quartus II device files (.qdz) on Quartus II 13.1
Hi, I'm trying to install device files for Quartus II 13.1 on Windows 7, but get the error "Can't find Quartus II Web Edition device files (.qdz) in directory ..." (see picture) quartuserror.jpg Did...
View ArticleAltASMI megafunction status read is shifted right by one
I use Altera AltASMI megafunciont for EPCS64 device with Stratix2 GX FPGA. My problem is When I read the Status register, I read status word shifted right by one. I also had this problem when I used...
View ArticleSynplifyPro for .vqm then Quartus P&R - Can't compile duplicate entity
I'm using Synplify Pro which compiles my .VHDL file and several Altera IP cores. The output is a .VQM. This is then input to Quartus for P&R. All scripts. quartus_sh is passed a .tcl file. It gives...
View ArticleQuartus fitter does not optimize as expected
Hi, I'm a seasoned ASIC designer but newbie in the FPGA field. Putting together a design, synthesis it and fit it a cyclone V went rather smooth but when I was looking at the result I thought it was a...
View ArticleStratix V Development board with QSFP ports
Hi, We have just bought a Bittware S5-PCIe-HQ development board which has a Stratix V FPGA. On the board are 2 QSFP+ ports. We wish to use these ports to transmit and receive data to and from the FPGA...
View ArticlePower Consumption Cyclone SXF - U23 vs F31 Package
Hi, I have the Altera Cyclone V SoC Dev Board, with which I measure the power consumption of the FPGA and HPS. Unfortunately for me the Cyclone V chip comes in the F31 package (896 pins). However, I...
View ArticleA Question About Constraints
I understand the clock constraining. But what about the non-clock signals. For example, I have a small VHDL design (1 file) that has a several clocks, a reset, and some LED output signals. The...
View ArticleSynplify Pro Cyclone V Part Numbers
Using Synplify Pro as a synthesis tool we pass it a project file that has all of the options and input files. One such option is the following which is wrong. set_option -technology CYCLONE V...
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