PLL changes as it ages?

We're using a Cyclone III LS FPGA in our design.

We're also using its internal PLL to shift a 120MHz input to a 240MHz clock.

Does anyone know if there is any data from Altera regarding how PLL performance changes as the FPGA ages?

Our customer has some question regarding how the waveform of the clock could change as time goes on.

Thanks in advance!