PLL changes as it ages?
We're using a Cyclone III LS FPGA in our design. We're also using its internal PLL to shift a 120MHz input to a 240MHz clock. Does anyone know if there is any data from Altera regarding how PLL...
View ArticleProblem using VHDL from a project lower in the heirarchy in an upper level
I created a very simple dual edge detector using D flip flops and a few logic gates. I created this using Megafunctions LPM_DFF, LPM_XOR, LPM_INV, and LPM_AND symbols. This project compiles and creates...
View Articleneed help with MIF file please
i am changing my MIF (rom Memory Initial File) context and it does not affect the rom out bus. i checked if it is the right rom file which belongs to the project. i saw by signal tap that there is no...
View Articlehow to convert Simulink model to VHDL, ,Matlab function using VHDL
Hope all is well, i am just wondering if any one has ever converted simulink model to VHDL codes, or has ever been able to write a matlab function using VHDL rather than c or c++
View Articlefloat_pkg help required
Hi folks, I want to use the float_pkg in my vhdl code to convert an integer to float (1 sign, 8 exp, 23 mantissa) to pass a value onto one of the float megafunctions provided by altera! However i cant...
View ArticleVHDL codes for battery charge & discharge and Control startegy used in Hybrid...
I am wondering if anyone has come across VHDL codes for a battery charge and discharge, I would like to make a circuit that control the battery charge and discharge and implement the control strategy...
View ArticleBRAM utilization and optimization
This is a two part question: First, how do you look at memory utilization in Quartus? I have a design that is only using ~65% of the memory bits in my device (according to the summary) but apparently...
View ArticleVIP build to build CVI stability
I'm building a VIP system that includes four video pipes that run simultaneously. Each pipe is displayed in a quadrant of the output display but one or more of the images is unstable. Each build...
View ArticleCyclone V bidirectional port OCT issues
Hi all, I'm trying to get series termination for a bidirectional bus instantiated in my Cyclone V. In assignment editor I've set the location, I/O standard(1.8V), and output Termination to series 25...
View Articleusing IP cameras through ethernet entries with fpga
hi all i've the DE2-115 board , and i want to connect a pair of cameras to the board. i thought of using IP cameras and connect them to the ethernet entries of the board. Is it feasable? can i get only...
View ArticleStratix V GX Development Card: Board Test System cannot detect USB Blaster
We have a Stratix V development card (5SGXEA7K2F40C2N) and cannot get the development kit GUI (Board Test System) to detect the USB Blaster. The USB blaster interface is recognized through Quartus...
View ArticleMemory for Nios II Software
I am using a 12K on chip memory for my Nios II system. In my software code, I am using an Integer array of length 500000. But I am wondering how it can be implemented on a 12k on chip memory?!!!. the...
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Interfacing to sld_hub
Hi, I'm trying to figure out an easy way to interface to sld_hub component. Basically, I'd like to replace the entire JTAG Tap Controller with the custom one. See the attached screenshot. Any ideas how...
View ArticleFuntion or something that finds the smaller integer
Hi, I'm looking for a simple way to find the smallest of a large number of integer signals (About 256) All I have right now is just 4 and I do as the code below, but it will grow up to 256 and I think...
View ArticleDE2 boards revisions ?
Hello I am an experienced SoC designer, with only little practice with Altera FPGA. To start with, I have designed a small circuit (for teaching purpose), that simulates and synthesizes correctly using...
View ArticleOn what CycloneIV Dev.Kit "PCI Express High Performance Reference Design" can...
Can "PCI Express High Performance Reference Design" be run on "Cyclone IV GX FPGA Development Kit" or only on "Cyclone IV GX Transceiver Starter Kit"? Deliverable from Altera "Download a PCI Express...
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0to16 counter with 2 resets
Hello For my project I need 0to16 counter with 2 additional inputs: reset singal sets the counter to 0, other one sets the counter to 8. I simulated my idea in simply application logisim and it worked...
View ArticleDE2 revisions (relocated here)
Hello I am new here in the forum. I made a mistake while asking my question about DE2 board revisions : I posted in the "Quartus II and EDA tools". Could you please have a look at it and preferably...
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Short Pulses on Incoming fronts creating asynchronously
Hi, I want to check pulses' fronts matching on two lines. These fronts are matched not ideally. The synchronous variant also would be tested (matching the fronts during one period of Fclk 200MHz), but...
View ArticleHelp understanding concepts in VHDL, like to use a FIFO
I need help understanding how to use a FIFO in VHDL. If I am inside a process and I want to put two bits serially into a FIFO, how is that done? I need to set the FIFO clock enable high, the write...
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