How will Altera ModelSim recognise RAM blocks
Hi guys, My question is regarding simulating a multi-port memory using QuartusII. I have the code given in the Recommended HDL Coding Styles chapter for a simple dual port ram. I have written the test...
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Never ending compilation, implosion of Quartus Map, compilation in modelsim...
Hi, I have an intresting issue with my VHDL code which I attached with some comments(logic3.vhd is the newest version). When compiling the code in quartus( I've tried versions 12sp2, 10.1 and 9.0 and...
View ArticleHow to download free evaluation of "IP Compiler for PCI Express (Hard IP)"?
At Altera web page "IP Compiler for PCI Express (Hard IP)" there is a link "Download Free Evaluation" which leads to Altera web page "Altera IP Library" which again after a search in "Alteras IP...
View ArticleThe difference between high-speed communication interface and protocol
I am confused by these two issues: interface and protocol, for a while. I try to understand their difference and want to discuss them here. Based on my understanding, interface determines hardware...
View ArticleOpenCore Plus license for Arm Cortexm1
Hi. I downloaded CortexM1_DevKit from ARM.com. I have the DE2_70 and neek fpga board. But i cant do synthesis. How can i get OpenCore Plus license for Arm Cortex-m1. No one does not reply to my emails....
View ArticleImplement HDMI, DVI, and DisplayPort input in FPGA
I investigate the feasibility of implement HDMI, DVI, and Displayport in a design. In this design, the FPGA will have the receiver for HDMI, DVI, and DisplayPort, to receive the signal comes from...
View ArticleDDR SDRAM pin assign problem
Hi, I'm trying to have a pin-assignment of EP3C55U484C7 with DDR SDRAM. I read the pin information for the Cyclone III EP3C55 device. but after assignment, threre are errors during compilation as "The...
View Articleperformance at -40C temp changes with minor design changes
We have a Cyclone III design that has 16 output lines we use for debug monitoring. For example we send out chip select and other control signals to the debug outputs which we monitor with a logic...
View ArticlePCIe as Soft-IP via CMU as transceiver in Stratix-IV
Hi, in a design using a Stratix-IV EP4SGX230KF40, all regular transceiver channels are already used for other connections, but I want to connect a PC-module via a PCIe 1.1 x1 link. Is this in any way...
View ArticleIIR filtering (bi-quad ORDERS 2)
Hi, Is there anyone who can tell me if Altera has a IIR filter (IIR Compiler or something else)? I'd like to have a simple Bi-Quad of order 2. I have the coefficients but not a structure in VHDL to use...
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ECO usage issues need you help
Hello all: I'm using ECO to modify my project manually. As attached file show, signal "|SEP2MCS|TDC_VJ:inst14|tdc_ctrl_set[0]" feeds into ALUT from DATAC, and "|SEP2MCS|SEP_TDC_7ch:inst13|inst19" feeds...
View Articleproblems with real data type conversion to std_logic_vector
Hi, I'm doing an discrete PID controller, based on FPGA's, but I wanna do it using floating point maths, the first block I was doing was an integrator, but I got an issue, the generic parameters of my...
View ArticleSBT 12.1 (Indigo) Problems with includes from bsp
Hi all, i updated the NIOS II SBT from 11-1SP2 to 12.1 and now all include-files which are located in my bsp are underlined red/orange an eclipse tells me that is is not able to resolve the inclusion....
View ArticleThe FPGA development board that supports supply scaling
Hi everyone, I am looking for a FPGA development board that can support adjusting the supply voltage or the supply voltage switches. Can anyone recommend me one? Thanks very much! Best,
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Power analysis in Quartus II 12.1 using PowePlay power analyzer
We have try to do the Power Analysis using Power Play Power Analyzer of Quartus II 12.1 Version. Can someone reply at these questions in the Image? Attached Images Power_Question.jpg (321.1 KB)
View ArticleThe general aproach to design high-speed serial communication in FPGA
Recently I try to learn how to design high-speed serial communication in FPGA. I don't have experience in this, so I think it is good for me to understand the general approach firstly. The general...
View ArticleUniversity program: simulation tools folder empty after installation
Hello all Please i've a problem with altera university program. i've quartus II 10.1 and i installed the corresponding setup of the universtity program. but i get the simulation folder empty ? and i...
View ArticleCIC Filter: code not compiling!
Hi, could someone please take a look at the code below and tell me why it is not compiling? Code: module cicdecim64 ( input clk, input reset, output reg clk2, input signed...
View Articleerror while simulating in quartus
Hi, I'm trying to simulate a FSM, but I keep getting this error message: "Error: Zero-time oscillation in node "|top|FSMcontrol:L1|Selector5~0" at time 50.0 ns. Check the design or vector source file...
View ArticleWhat resources does my block consume?
This is probably very simple, so simple that it is not in faq or help. I just generated an instance with MegaWizzard and would like to know what resources this new block uses. Also I would like to see...
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