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TimeQuest Constraints Automation
Hi all, Altera's site has the page "Simplify Design Reuse with Dynamic SDC Constraints" http://www.altera.com/support/exampl...clock-sdc.html which intriguingly implies that SDC constraints files can...
View ArticleHDMI Output with Cyclone IV
Hello, i was looked at the forum and could not find this answer. Is it possible to drive an HDMI port directly from a Cyclone IV as it is possible with Xilinx Spartan 6? Regards, LR
View Articlec2h error at bitmap header declaration
Hi, I am trying to accelerate a function func_acc(). However i am getting an error during the c2h compilation. What puzzles me is that the error is triggered at the main() function, not even at the...
View ArticleStrength
Hello everybody, I have a question regarding the use of the strength of the signals(highz, small, medium, weak, large, pull, strong, supply) As far as I understand if 2 signals with 2 different...
View Articlepcie jungo driver for 64 bit system
am using PCIe jungo driver for my PCIe project read/write operation in 32 bit system it is working, is there any Jungo driver software which supports for 64 bit system. please send the link
View ArticleI need help with simulation by ModelSim
Hello As written in title, I am trying to do RTL simulation using ModelSim and stuck with it. I'm a newbie to ModelSim and this question may seem stupid, but please help me (I looked for a lot of "How...
View ArticleVcd file : Variable or signal?
What is the difference between variable and signal in a VHDL file? Why the variable are not included within vcd file? Is it a problem in the Power Analyzer phase?:cry::p:cool:
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"Simple Socket Server" demo code stop after display "simple socket server...
Dear Friend's i am using DE2_115 board and over that i am running Simple Socket Server Example, i just strip out LED and 7-Seg Show Task's from my Code and compile it but when i run this peace of code,...
View Articleusing integer
Hi, I have two questions about using integer in VHDL. 1. If I had to convert a std_logic_vector to an integer, is it better to use CONV_INTEGER(MyVector) or to_integer(unsigned(MyVector)) ?? Or is it...
View ArticleCyclone III FPGA Temperature Measurement.....
Hi All, I want to measure the temperature across the cyclone III fpga. Is there any inbuilt sensor is available for the temperature measurement? If yes please let me know the procedure to measure using...
View Articledsp_block_balancing
Hi, in my design, I have 2 integer multiplications. After synthesis I saw that the timing requirements are not met. And I saw that NO DSP Elements were used despite of the 2 multiplications and several...
View ArticleSD Card IP Core : timing constraints questions
Hello, I'm using the Altera SD Card IP Core with Nios II, and I have a few questions regarding the timing constraints. The Doc says : Quote: Finally, it is important to set Tco and Tsu constraints for...
View ArticleHow to get the default modelsim.ini file back？
I compiled the libraries of FPGA and get a new modelsim.ini file in complied directory. Then I directly copy this file into modelsim installation directory. The default one has been replaced. Then I...
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Signal tap II issue
Please check the attached image, why some signals are fuzzy? They supposed should be clean "low" or "high" Many Thanks. Untitled.jpg Attached Images Untitled.jpg (269.7 KB)
View ArticleRF Transceiver Chip
My final year project is relates building a device that will transmit and receive AIS and VHF DSC signals from the man in distress to the rescue team and as a result, I am trying to find an RF...
View ArticleProgram MAX V via .svf file
Hi folks, I am evaluating a MAX V CPLD for a small university project, although I have not much experience with CPLDs, yet. As I understood, the Quartus software generates file containing a description...
View ArticleSimulating NiosII Design in ModelSim \ Active-HDL with breakpoints
Hey everyone! I want to simulate my NiosII software built with NiosII IDE with a simulation software (ModelSim \ Active-HDL). I've done some research over several sites and doesn't find any information...
View ArticleError: CONF_DONE failed to go high in device 1.
Before anyone comments on this, I have searched the forum and read everything I have found on the internet with people getting this error message. :) I'll try to post as much relevant information as...
View Articlenios2 is missing.
HiI have this problem:i am following altera buildroor guide (http://www.alterawiki.com/wiki/Buildroot_Guide), but after command MAKE MENUCONFIG, in Target Architecture, nios2 is missing.Can i help me...
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