using integer

Hi,

I have two questions about using integer in VHDL.

1. If I had to convert a std_logic_vector to an integer, is it better to use CONV_INTEGER(MyVector) or to_integer(unsigned(MyVector)) ?? Or is it the same?

2. If I had to communicate integer values between to blocks, should I use an Integer OUT / IN, or is it better to convert to std_logic_vector and reconvert to integer??

Thanks for your answers!
Sim