_tb has no architecture (error in modelsim(of altera)(14.0)), plz help

simple program and its testbench(copy from book of volnei a. pedroni 2 e)
----------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------
ENTITY mydesign_tb IS
END ENTITY;
--------------------------
ARCHITECTURE testbench OF mydesign_tb IS
---DUT declaration:------
COMPONENT mydesign IS
PORT (clk, rst, din: IN STD_LOGIC;
dout: OUT STD_LOGIC);
END COMPONENT;
----signal declarations:-----
SIGNAL clk: STD_LOGIC := '0';
SIGNAL rst: STD_LOGIC := '1';
SIGNAL din: STD_LOGIC := '0';
BEGIN
---DUT instantiation:-----
dut: mydesign PORT MAP (clk, rst, din, dout);
----stimuli generation:-----
clk <= NOT clk AFTER 40ns;
rst <= '0' AFTER 80ns;
din <= '1' AFTER 160ns, '0' AFTER
240ns, '1' AFTER 32ns;
END ARCHITECTURE;
-----------------------
--------------------------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------
ENTITY mydesign IS
PORT (clk, rst, din: IN STD_LOGIC;
dout: OUT STD_LOGIC);
END ENTITY;
----------------------
ARCHITECTURE mydesign OF mydesign IS
BEGIN
PROCESS (clk, rst)
VARIABLE q: STD_LOGIC_VECTOR(0 TO 3);
BEGIN
IF (rst='1') THEN
q := (OTHERS => '0');
ELSIF (clk'EVENT AND clk='1') THEN
q := din & q(0 TO 2);
END IF;
dout <= q(3);
END PROCESS;
END ARCHITECTURE;
------------------------------
but when I try to compile(both, error on tb-"unknown identifier dout") and simulate tb, error about no architecture of tb on my altera modelsim 14.0 on linux-ubuntu 14.04. plz help, eric