Problem with the Evalboard Terasic DE0_Nano with the AlterA Cyclone...
Hi guys, i have another problem with the Terasic Evalboard DE0_Nano with the AlterA Cyclone EP4CE22F17C6N. I start the Demonstration DE0_Nano_SOPC_DEMO. After succesful Generating of the qip files and...
View ArticleInstalling Devices on Quartus II Web Edition (Free)
I downloaded the combined files and installed Quartus II (14.0.0.300 64-bit) on my PC. I can't open a project unless I install the devices. The install dialogue asks for the directory that "contains...
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Altera Monitor Program issue on Win7 Pro (64-bit) (fresh install)
My desktop (not the machine mentioned in the title) had been working fine with Quartus, but when my class go to the point where we were going to work with assembly, AMP is having some issues. After...
View ArticleTransceiver placement issue
Hi, There is one block, four transceivers in an EP4CGX22 FPGA chip. If i need to use it to design two independent transceiver links, each one with 2 transceiver channel bonded, is it OK? Thanks a lot....
View ArticleTimeQuest User Guide Question
I have a question regarding the virtual clock assignment described in the TimeQuest User's Guide on the web. I am not sure I understand how the virtual clock created for the set_input_delay and...
View ArticleWhy do I see termination logic option errors when I turn on design partitions?
Using QII 14.0. My design successfully compiles when I turn of design partitions. But when I turn on design partition I get following error - Error (169172): Output pin "adc_sense[2]" specifies a...
View ArticleSDC Constraints for Asynchronous Interfaces
I am trying to constrain some asynchronous interfaces which my FPGA interfaces to. I have a single FPGA clock, CLK_FPGA (period = 20ns) which clocks all logic in the FPGA. One asynchronous interface is...
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Arrow SoCKit Linaro Desktop with ACDS 14.0 and Linux 3.13
Hi, I thought I'd provide some tips on using Arrow SoCKit Linaro Linux Desktop on ACDS 14.0, as I got it working just recently. This assumes you already have this one installed successfully:...
View ArticleCAS Latency on Cyclone V DDR2 Hard Memory Controller
When running simulations using the Cyclone V DDR2 HMC UNIPHY simulation model I noticed something very strange. If I set the CAS latency to 7, data is written correctly. If I reconfigure HMC to CASL=5,...
View ArticleΠληρους...
Θα ηθελα την βοηθεια σας σχετικα με την ένωση ενος Πλήρη αθροιστή του ενός bit χρησιμοποιώντας ένα αποκωδικοποιητή active low 3x8 (ολοκληρωμένο 74138) στο Quartus. Με ειδοδους Α,Β, Cin και εξοδους Cout...
View ArticleCycloneIV adder behavior
Hi everyone, I have a snippet of code that adds. Code: logic bitCount[3:0]; always_ff @ (negedge sck, posedge cs) begin if (cs) bitCount <= 4'b0000; else...
View Article_tb has no architecture (error in modelsim(of altera)(14.0)), plz help
simple program and its testbench(copy from book of volnei a. pedroni 2 e) ---------------- LIBRARY ieee; USE ieee.std_logic_1164.all; ------------------ ENTITY mydesign_tb IS END ENTITY;...
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Hard emi, Cyclone V SX, max speed
Hello. Who used Hard External Memory Interface on Cyclone V SX(Arrow SocKit board)? I can't get speed more than 140mbit/s via HPS2FPGA bridge with hard emi. With softcontroller I get a speed of around...
View ArticleQuartus Convert Partial Reconfiguration Programming Files
I am attempting to replicate the example provided on the Altera Wiki for partial reconfiguration. I compile using the provided .tcl file, and the only modification I make is to add a quartus.ini file...
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Combining similar elements to single combo logic cell after Quartus compilation
I have a question: How I can disable combining similar elements to single combo logic cell after Quartus compilation process. For example: I have a project like screenshot ("1-block_diagram.jpg" in...
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Hello World example produces many errors
Hello, I am doing research using openCL at my university and we do not have a physical board. My openCL compiler runs, by using the reference board s5_ref, but it produces many errors, so then I...
View ArticleSCFIFO wrreq and rdreq synchronisation
Hi folks, just a quick question (hopefully), In the SCFIFO megafunction I want to know if the wrreq and rdreq signals are synchronised to the clock input. That is to say, if I clock the FIFO with my...
View ArticleEnable L2 Cache
Hi! Is there an simple(!) example on using the L2 Cache (using hwlib)? My current test project places some code(some few KB) at 32MB offset (0x0200 0000), so i guess it ends up in DDR Ram. All...
View ArticleMysterious sopc_altera_pll directories in my home directory
I have been noticing that empty directories are getting created in my home directory when I run ip-generate. The directories have names of the form sopc_altera_pll<secs><digits> where...
View ArticleInterfacing with Altera-MM Salve of UniPHY DDR2 controller
Hi to all.... This is my first post in this forum and my english is not quite good... I have some problem with a UniPHY interface generated trought Megawizard (Quartus II 13.0 with a Stratix IV device)...
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