DDR3L on cyclone V E (HMC)
Does the cyclone V (5CEFA4F23I7) support DDR3L in Hard Memory Controller ? Handbook says: The SDRAM controller offers the following features: Low-voltage 1.35V DDR3L and 1.2V DDR3U support. But it...
View Articlesequential circuit power
I request you to let me know the following. i have sequential circuit consuming p mW using PowerAnalyzer in Quartus II. I duplicate the sequential circuit. I find that power is now q mW where q is not...
View Articlejpeg image library code in verilog
I need jpeg image library code in verilog for read an image in the sram memory.
View ArticleMODELSIM error vsim-3807
Hi folks, I have recently encountered a problem which I have not seen before, even though I am following the same design/synth/sim flow as I usually do. Basically, when I go to RTL simulate in MODELSIM...
View ArticleBaremetal appication(LED Blinking)
Hello, Am working with Macnica Helio SoC kit. Am using Helio kit's Golden Hardware design in quartus. Can anyone help me with the following issues. 1) How to develop a Baremetal application blink the...
View ArticleRefreshing older FPGA with Avalon OpenCores 10/100 Ethernet MAC
Hello! We are working on an FPGA with the older Avalon OpenCores 10/100 Ethernet MAC (v8.02) which was completed in ~2009 using Quartus 8.x and SOPC builder on a Cyclone III. We have ported the...
View ArticleQuestion about warning: "Port type is incompatible with connection (port...
The warning was issued after simulating a module written by Verilog. # Region: /.../.../.../u1/lpm_mult_component # ** Warning: (vsim-3016) C:/.../.../.../multiplier.v(62): Port type is incompatible...
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Using QDRII with NIOS
I want to use the QDRII SRAM on the Arria V GT dev board as memory for a NIOS processor. The QDR has separate Avalon MM ports for read and write, but I think they must be assigned the same address...
View ArticleQuestion regarding loading the SRAM with .ram files and additional .sof file
Greetings, In one of our course project, we are to design a small processor which requires instructions to be fetched from the SRAM memory. The procedure given is as follows: 1. We open the...
View ArticleDebugging with the Nios II 14.0 Software Build Tools
I am unable to debug in the Nios II 14.0 Software Build Tools for Eclipse environment. Attempting to do so produces these messages:'Launching ... configurtion' has encountered a problem. Error starting...
View ArticleSoC Dev Kit Quality of Experience Survey
Have an opinion about the Altera SoC development kits? We would like to hear it! Please click here to tell us what you liked, what you didn't like, and what you would like to see improved....
View ArticleSoC Dev Kit Quality of Experience Survey
Have an opinion about the Altera SoC development kits? We would like to hear it! Please click here to tell us what you liked, what you didn't like, and what you would like to see improved....
View ArticleDiagnose AOC: Internal Compiler Error
Hi all, I've been using the Altera OpenCL SDK for about a month now with no issues, but suddenly I have come across the dreaded "Error: Internal Compiler Error" prompt. The last thing I would like to...
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Problem with SOPC to QSys Migration
Hello everyone! I'm extremely new with the Quartus Software, and I'm assisting a person with simple tasks. I was asked to investigate how to migrate SOPC to Qsys, which I did and eventhough I had never...
View ArticleLogical operation on vectors
I am trying to compile the following, simple kernel: __kernel void foo() { ulong2 l1 = (ulong2)(1UL, 1UL); ulong2 l2 = (ulong2)(2UL, 2UL); l1 && l2; } I'm using the following command to...
View ArticleMultiple (concatenated) DDR3 interface
Hello - I am looking to design a DDR3 controller that interfaces to two 16-bit wide DDR3 memory devices as one 32-bit interface. On our board we plan to share address and control lines for the two...
View ArticleStratix V QDR-II+ Controller PLL won't lock
We have a 5SGSED6N3F45C4N on a custom board connected to a Cypress CY7C2663KV18 QDR-II+ memory. We're providing a 100 MHz 1.5V DHSTL reference clock FPGA device pins BC8 and BD8 (the CLK11 pair) and...
View ArticleVersion control for the Quartus project
For project built in the Quartus, what files I need to commit to version control system? For HDL and sdc files are straightforward, how about files related IPs? Meanwhile, what is the best approach for...
View Articlemodelsim vlog error syntax error, unexpected IDENTIFIER, expecting clocking
I cannot compile one of my verilog files in modelsim altera edition. I get this error using the global primitive. # ** Error: (390): near "b2v_inst1": syntax error, unexpected IDENTIFIER, expecting...
View ArticleDTB (Device Tree Blob Files) Step by Step Guide DE1-SoC ** HELP ! ** GPIO Q14.0
I am developing a design on the DE1-SoC. I wanted to be able to drive some more GPIO from the HPS. The pins that were already GPIO in the GHRD work fine. After clicking the button in the HPS tab in...
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