I cannot compile one of my verilog files in modelsim altera edition. I get this error using the global primitive.
# ** Error: (390): near "b2v_inst1": syntax error, unexpected IDENTIFIER, expecting clocking
global b2v_inst1( .in(LCLK1), .out(g_lclk1_c0));
Any ideas on how to fix ?
Thanks.
# ** Error: (390): near "b2v_inst1": syntax error, unexpected IDENTIFIER, expecting clocking
global b2v_inst1( .in(LCLK1), .out(g_lclk1_c0));
Any ideas on how to fix ?
Thanks.