Question about warning: "Port type is incompatible with connection (port 'clock')"

The warning was issued after simulating a module written by Verilog.

# Region: /.../.../.../u1/lpm_mult_component
# ** Warning: (vsim-3016) C:/.../.../.../multiplier.v(62): Port type is incompatible with connection (port 'clock').

The module has a clock input "clk" which is assigned directly to a multipier generated by the megafunction. The warning refers to the "clock" signal within the multiplier.

I don't understand why this warning was issued since the "clk" signal is defined as "input" and the "clock" signal within the multiplier is defined as "input" by the megafunction. Port type should be compatible.


Any suggestion please?