I want to use the QDRII SRAM on the Arria V GT dev board as memory for a NIOS processor. The QDR has separate Avalon MM ports for read and write, but I think they must be assigned the same address range to work as NIOS memory. But Qsys complains about address overlap. It seems Qsys doesn't understand a read-only or write-only Avalon slave, so it thinks they conflict. Qsys view is attached.
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