Hi folks,
just a quick question (hopefully),
In the SCFIFO megafunction I want to know if the wrreq and rdreq signals are synchronised to the clock input. That is to say, if I clock the FIFO with my system synchronous clock, but make a write request to the fifo from an asynchronous source, does the megafunction sync it to my system clock for me, or am i expected to put in a two stage sync myself?
likewise for the rdreq signal?
The user guide seems to suggest that it is done for me, but I wasnt entirely sure!
many thanks for any advice.
deBoogle
just a quick question (hopefully),
In the SCFIFO megafunction I want to know if the wrreq and rdreq signals are synchronised to the clock input. That is to say, if I clock the FIFO with my system synchronous clock, but make a write request to the fifo from an asynchronous source, does the megafunction sync it to my system clock for me, or am i expected to put in a two stage sync myself?
likewise for the rdreq signal?
The user guide seems to suggest that it is done for me, but I wasnt entirely sure!
many thanks for any advice.
deBoogle