I've been working on FPGAs now for a year or so - building my own Atari 800XL clone in hardware. This is running on several boards using pure VHDL, except for the PLL. On all other boards I'm using a ZPU as a support CPU to do drive emulation etc.
I'm now trying to get this running on the Arrow SOCkit board. So far I have the FPGA side working, using block RAM and no communication with the ARM (programming sof via JTAG). I also have the HPS side working in that it boots/runs linux ok. I'm using Quartus 14.1 under Linux. So for the next step I'd like to get both working together.
Here I'm running into issues. I've tried following Howard Mao's tutorial and am stuck on section III, where it starts to include the HPS. I've followed his example on how to create the QSYS setup with the lightweight HPS->FPGA bridge. So far so good...
Then I hit several problems.
Problem 1:
So I include the .qip file, and attempt to add the component to my vhdl top level. The first problem is that I can not instantiate the component by the usual method:
system 1: entity work.mysystem
port map...
or
system 1: entity mysystem.mysystem
port map...
So I solve this by creating a component/end component block then instantiating with:
system 1: mysystem
It seems there must be a vhdl library that the altera ip components are in, I just can not work out what is it. Which library are the altera ip components in? How can I instantiate it with entity syntax?
Problem 2:
The main showstopper...
The qsys system has a bunch of sdram like signals exported. I gather from the tutorial that I'm meant to simply connect these to my top-level with the same names, then the sdram tcl pin assignment script will magically create assignments for me. This script does indeed create some pin settings, however no pin assignments. So when I build it I get a fitter error about lots of pins not having explicit locations. Are these HPS QSys pins real pins assignements? Or 'internal pins' that connect the FPGA to the HPS? How can I solve this?
Problem 3:
I'm not really clear on what the HPS QSys pins I'm connecting are... I've tried setting up HPS in two ways -
i) as Howard described - i.e. setting up very little - this gives an 8-bit SDRAM type interface.
ii) As described in the SOCkit hardware lab - with detailed Micron SDRAM timings, board timings, HPS components. Now the latter gives me many more pins to assign in my top level. Which again the fitter can't find. However what I do not understand it - the HPS is already running Linux. If I program the FPGA am I actually changing HPS SDRAM settings and wiring? Linux is expected to keep running through this? Or are all the HPS settings except the bridges ignored when programming the FPGA from linux?
Problem 4:
Clock domains... QSys has a clock input. Is this just used for the fpga bridges and I can use what I like? I have a very specific PLL clock to have exact PAL or NTSC frequencies and am wondering if my avalon MM slave can directly use this frequency? Or if I need to match the slave frequency to the HPS?
I'm pulling my hair out trying to figure these out, so any advice will be greatly appreciated. If anyone has a _minimal_ vhdl QSys example with just a slave e.g. using LEDs etc I'd be very interested to see it. I could build my project on top of a Hello World like that I guess, but for now I've not had any luck getting examples running.
I'm now trying to get this running on the Arrow SOCkit board. So far I have the FPGA side working, using block RAM and no communication with the ARM (programming sof via JTAG). I also have the HPS side working in that it boots/runs linux ok. I'm using Quartus 14.1 under Linux. So for the next step I'd like to get both working together.
Here I'm running into issues. I've tried following Howard Mao's tutorial and am stuck on section III, where it starts to include the HPS. I've followed his example on how to create the QSYS setup with the lightweight HPS->FPGA bridge. So far so good...
Then I hit several problems.
Problem 1:
So I include the .qip file, and attempt to add the component to my vhdl top level. The first problem is that I can not instantiate the component by the usual method:
system 1: entity work.mysystem
port map...
or
system 1: entity mysystem.mysystem
port map...
So I solve this by creating a component/end component block then instantiating with:
system 1: mysystem
It seems there must be a vhdl library that the altera ip components are in, I just can not work out what is it. Which library are the altera ip components in? How can I instantiate it with entity syntax?
Problem 2:
The main showstopper...
The qsys system has a bunch of sdram like signals exported. I gather from the tutorial that I'm meant to simply connect these to my top-level with the same names, then the sdram tcl pin assignment script will magically create assignments for me. This script does indeed create some pin settings, however no pin assignments. So when I build it I get a fitter error about lots of pins not having explicit locations. Are these HPS QSys pins real pins assignements? Or 'internal pins' that connect the FPGA to the HPS? How can I solve this?
Problem 3:
I'm not really clear on what the HPS QSys pins I'm connecting are... I've tried setting up HPS in two ways -
i) as Howard described - i.e. setting up very little - this gives an 8-bit SDRAM type interface.
ii) As described in the SOCkit hardware lab - with detailed Micron SDRAM timings, board timings, HPS components. Now the latter gives me many more pins to assign in my top level. Which again the fitter can't find. However what I do not understand it - the HPS is already running Linux. If I program the FPGA am I actually changing HPS SDRAM settings and wiring? Linux is expected to keep running through this? Or are all the HPS settings except the bridges ignored when programming the FPGA from linux?
Problem 4:
Clock domains... QSys has a clock input. Is this just used for the fpga bridges and I can use what I like? I have a very specific PLL clock to have exact PAL or NTSC frequencies and am wondering if my avalon MM slave can directly use this frequency? Or if I need to match the slave frequency to the HPS?
I'm pulling my hair out trying to figure these out, so any advice will be greatly appreciated. If anyone has a _minimal_ vhdl QSys example with just a slave e.g. using LEDs etc I'd be very interested to see it. I could build my project on top of a Hello World like that I guess, but for now I've not had any luck getting examples running.