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Preloader execution issues / Arrow SoCkit board
Hi, I try to setup DDR3 SDRAM from HPS on my Arrow SoCkit and then run bare metal application on it. I've installed HPS component in Qsys, set SDRAM controller parameters, make pins assignments with...
View ArticleSOCkit Hard Processor System - problems getting started (unassigned pins,...
I've been working on FPGAs now for a year or so - building my own Atari 800XL clone in hardware. This is running on several boards using pure VHDL, except for the PLL. On all other boards I'm using a...
View ArticleQuartus II 12.0 : Timing closure and register retiming
I am new to FPGA programming and quartus. I am unable to fix the timing closure issue. I get Worst case slack is -3.038. I am trying to make use of register retiming using a pipelined multiplier....
View ArticleCyclone V hard memory controller clarification
Hi, I'm relatively new to this stuff but have spent a few weeks getting to the point of understanding how fast I can stream data into DDR3 sdram on a cyclone V reference design (bemicro-CV). I started...
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Cyclone V and QSYSa)
Hi, I am trying to create a system on a Cyclone V development board. I attached a pdf file that shows what I am trying to do with the sytem. I want to create this in Qsys, and I have questions about...
View ArticleTristate outputs - how to?
Hi, I want to tristate a group of outputs based on the state of an input pin (MAX7000S). I have found the TRI megafunction but it looks like this uses additional resources that shouldn't be necessary....
View ArticleSystem Console crash - Quartus II 14.1 and Win 8.1
Hi everybody, Yesterday I installed Quartus II 14.1 on my new Windows 8.1 computer. On my previous computer I have used Quartus 12 with no issues (W7 32bits). The new computer has the latest Microsoft...
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Avalon bridge question
Hi. I'm trying to build a system with address decoding in Qsys. What I want (see the picture) - I want address BRAMs using one big address (with auto decoding). I can add an AXI bridge to Qsys with the...
View ArticleALTFP_MULT always return 0
Hi everyone, I'm new to fpga/verilog and met a weird problem when using altfp_mult ip core. --------------------------------- I am using de2i-150 developing board, which has an Intel Atom CPU and a...
View ArticleMAX7000 programming question
Hello, please advise - I am starting using MAX7000S device - PLCC44. It has 8 power pins, 4 JTAG pins and 32 user i/o pins. I needed more than 32 pins for i/o, and disabled "JTAG BST support", giving...
View ArticleCyclone lll emulated LVDS IO
Hi, Currently, we are using Cyclone lll FPGA for our application. We plan to interface LVDS output signals with sensor chip. We had assigned LVDS related O/P signal in bank 7 and bank 8(top banks). As...
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Quartus II 14.0 compile time too long
Hi, I use quartus II 14.0 (linux 64bit version) to compile my design and my deive is Arria V ((5AGXB3H4F35C4). The compile time is about 4 hours. I think that My PC is powerful. The compile message is...
View ArticleModelSim on Fedora 20
Hi, I've installed ModelSim into my fedora 20, and when I change the directory to: /altera/14.1/modelsim_ase/linuxaloem/ And I tried to run ModelSim with command: ./vsim But there were errors pop...
View ArticleLast web edition to support Stratix III and parallel compilation?
Hi! Can anyone provide some information about this? Currently i have 9.1 SP 1. I would like to find web edition with Stratix III support and parallel compilation. Thank you!
View ArticleInput audio file into altera DE1 kit
Hi, Can i direct inputting audio files like .mp3 file into Altera DE1 kit or i must input the audio via using microphone? Any useful steps or simple coding to do so?
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PWM Schematic does not work
Dear helpful guys, I am a newbie who has started working with Quartus... In the appendix I have saved a picture of my schematic and also the Altera application note as PDF for the circuit I want to...
View ArticleDDR3 support hard mem controller Cylopne V SOC
Is DDR3 support, using the Cyclone V soc hard controller, limited to certain speed grades?
View ArticleAltera Cyclone V PLL in zdbfbclk configuration
Hi, I've recently started using Altera's PLLs for a Cyclone V project. I'm creating a PLL, with the IP Wizard, with zero-delay buffer (zdbfbclk) mode enabled. I want to use the zdbfbclk port to drive...
View Article[Transceiver toolkit] Reference clock trouble
Software: Quartus II 13.1 (64bit) Device: 5SGXE7N2F40C2 Kit: Stratix V GX Edition Transceivr Sigal Integrity Kit PC OS : Windows server 2012 64bit & windows 7 64bit Nice to mee you. My name is...
View Articleabout Nios® II Boot from EPCQ or EPCS in Quartus® II 13.1
Nios® II Boot from EPCQ or EPCS in Quartus® II 13.1I want boot from EPCQ128 in Quartus II 13.1. I have read the resolution rd11192013_118 and meet some problem when generate .flash files with elf...
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