Cyclone V and QSYSa)

Hi,

I am trying to create a system on a Cyclone V development board. I attached a pdf file that shows what I am trying to do with the sytem.
I want to create this in Qsys, and I have questions about what I can and can't do with the components.


I have seen Dave's reference design, and it helped quite a bit.
go to http://www.alteraforum.com/forum/showthread.php?t=43992
Dave I posted a DDR3 example for the BeMicro-CV board in this thread - scroll down to Post#5



Please refer to the attached diagram in relation to the questions below.

1) Can I wire up the DMA controllers as shown? In particular, how do I connect them to the PCIe controller. I used a Gen 1 PCIe controller, because it can have 8 functions.

2) Exactly how do I connect the DMA controllers to the PCIe controller? The Altera example (ep_g1x4.qsys) shows the DMA_0 read master and write master both connecting to the PCIe Txs port.
a) Do I need some type of buffer to isolate the DMA's from the PCIe and each other? It seems that if I connect both DMA ports to the PCIe Txs port, by default I have shorted the 2 banks of SDRAM.
b) How do I connect the DMA controller slave (configuration) ports? The example shows dma_0 connected to Rxm_BAR2. would I connect dma_1 to Rxm_BAR3 (seems like the logical choice).

Any help would be GREATLY appreciated.


Thank you.

Attached Files

• Block-D_Data-Flow.pdf (64.3 KB)