Hi,
I'm relatively new to this stuff but have spent a few weeks getting to the point of understanding how fast I can stream data into DDR3 sdram on a cyclone V reference design (bemicro-CV). I started with the basic configuration from Dave (posted elsewhere on these forums) (dwh@ caltech) -- and struggled through getting to the point where i got things working with the custom logic I added to it (the example project was a great way to get going).
I found that the memory controller couldn't seem to keep up above the 80% bandwidth efficiency point( BMCV has 16 bit bus, 333 MHz DDR, so ~ 10.6G =max ignoring refreshes and other overhead).
Does this KB article explain that? I just want confirmation that this is indeed the case.
http://www.altera.com/support/kdb/so...02012_952.html
I am using two ports on the memory controller MPFE (one hooked to JTAG per Dave's project, the other to my custom logic that basically stuffs a timer value into things using a wide avalon MM interface with long bursts). I tried long and short bursts and the point of failure was always right at about the same point. After some digging, I found this note about the hard IP and am pretty sure this explains the problem.
I believe I could push a little further by trying to load both ports, but for my design I'm not sure it is worth it, I more or less want to just understand the limitations at this point.
Thanks for any input / confirmation!
Lance
I'm relatively new to this stuff but have spent a few weeks getting to the point of understanding how fast I can stream data into DDR3 sdram on a cyclone V reference design (bemicro-CV). I started with the basic configuration from Dave (posted elsewhere on these forums) (dwh@ caltech) -- and struggled through getting to the point where i got things working with the custom logic I added to it (the example project was a great way to get going).
I found that the memory controller couldn't seem to keep up above the 80% bandwidth efficiency point( BMCV has 16 bit bus, 333 MHz DDR, so ~ 10.6G =max ignoring refreshes and other overhead).
Does this KB article explain that? I just want confirmation that this is indeed the case.
http://www.altera.com/support/kdb/so...02012_952.html
I am using two ports on the memory controller MPFE (one hooked to JTAG per Dave's project, the other to my custom logic that basically stuffs a timer value into things using a wide avalon MM interface with long bursts). I tried long and short bursts and the point of failure was always right at about the same point. After some digging, I found this note about the hard IP and am pretty sure this explains the problem.
I believe I could push a little further by trying to load both ports, but for my design I'm not sure it is worth it, I more or less want to just understand the limitations at this point.
Thanks for any input / confirmation!
Lance