STA and Timequest relation

Hello everyone, i am fresher to VLSI fiels. I am doing Verilog/VHDL coding for last 10 months. I come across these back end terms of Constraining, Timing and fitting the design on FPGA. I read about them on internet like what constrains do, STA is important and can be done on different level and other information. I have few questions based on that Hope u reply and put me out of my curiosity.

1. What does TimeQuest do?
2. Difference between constraining the design and performing STA?
3. I am fresher, so how to know what values to put in constrain column?
4. How STA is performed?

Help me out, i will study and work hard JUST GUIDE ME.