JTAG prgramming is not working in my Cyclone 4 based board.
Hi all, I'm new to this forum. I have one issue in my Cyclone 4 (EP4CE6E22C8N) based development board.. Please provide some basic tips. FYI: TDI, TMS pins of the JTAG connector always LOW (even I have...
View ArticleStratix IV GX : Recovering the preloaded jic
Hi all, I have erased the preloaded jic from Stratix IV GX development board. Is there a way to reload it? Where can find the jic?
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Error: top level design entity "adc_system" is undefined / Pin Assignment for...
Hello everybody!!! Is it that there's an error in the Tutorial "Using the DE0-Nano ADC Controller"? Using the code on page 10, starting Analysis & Synthesis results in the error "top level design...
View ArticleDifference among Qsys Sim model, test-bench Qsys sys and test-bench Sim model
I'm confused about the purposes of different models that are offered during the generation process. In 'Generation' window you can have: 1) Simulation model 2) Test-bench Qsys system 3) Test-bench...
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error in pin planner
hello all, i got one error in pin planner that is Error (176172): Can't place node "hsync_n" -- node is a differential I/O node. with this post i am attached .Qsf file. i dont know why this error comes...
View Articlecan i read 2 input analog in DE0 nano without switch selector???
i read the manual book that explain DE0 nano have IC ADC to read analog data but it's just can access 1 pin in one time using a switch selector, then i read the program demo on deo nano sample itls...
View ArticleVIP core simulation error
hi, everyone. I am trying to simulate VIP-IP core. when I tried to simulate the core with Qsys model-sim gave me some errors those are like. .../db/ip/camCore/camCore.v(32): Module parameter...
View ArticleI cannot generate .sof file
Hi! i create a simple project in quartus ii v7.2, it containe a schematic file with three gates. I compiled it but haven't generated the .sof file. So, when i go to load my project to the board there...
View ArticleCould find (down load MAX+PLUS ii baseline version 10.0
Hi, I woring with maintenance of old industrial equipment and many time need to upgrade FPGA (7000S serie). To migret to windows 2000 or XP I need to start with max+plus 10.0 that still alloes using...
View ArticleResults of Verilog debugging problems
The design of a level sensitive latches, input signal is d clock, the output for the Q, the function is clock=1, q=d My code is as follows, the problem is the simulation results in clock=1, q=d no...
View Articlecan i read 2 input analog in DE0 nano without switch selector???
i read the manual book that explain DE0 nano have IC ADC to read analog data but it's just can access 1 pin in one time using a switch selector, then i read the program demo on deo nano sample itls...
View ArticleHow to implement a 32K lookup table in CPLD?
hello, I'm newbie in VHDL, FPGAs and CPLDs devices. I would like some help for implement a lookup table with 2048 words (2 bytes). The table should be: 2048x16bits (32K), I mean, 11 bits address...
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[Question about synchronous transfer] Will this kind of transfer cause problem?
I know for any asynchronous data transfers, we would need special handling mechanisms (i.e double sync, FIFO, handshaking, etc). I have a design that where the core logic interacts with the LVDS TX IP...
View ArticleEndianess of Avalon-ST Packets to PCI Express TLPs for IP Compiler for PCI...
Hi, we are using PCIE Express Hard IP to interface both PowerPC and Intel X86. The difference that influences our FPGA user logic is the endianness of two processors. PowerPC is Big endian while Intel...
View ArticleEndianess of Avalon-ST Packets to PCI Express TLPs for IP Compiler for PCI...
Hi, we are using PCIE Express Hard IP to interface both PowerPC and Intel X86. The difference that influences our FPGA user logic is the endianness of two processors. PowerPC is Big endian while Intel...
View ArticleSTA and Timequest relation
Hello everyone, i am fresher to VLSI fiels. I am doing Verilog/VHDL coding for last 10 months. I come across these back end terms of Constraining, Timing and fitting the design on FPGA. I read about...
View ArticleCyclone iii developpment board: DVI problem
Hello all, I create a Sopc system to test my dvi output but it does'nt work. I use a test pattern and a clocked video output, it's a simple system. I use a clock of 108Mhz for a resolution of...
View Articlevip_top for video example design
Hello all, I want to to use the eample design video donné par altera but I can't find the .bdf file that contains the graphic modules. I f someone have this example please I need it. Cordially
View ArticlePLL Locking - Transient input clock
Hello, I am hoping someone can offer a bit of advice with respect to using a PLL to lock to a clock that is transient. Currently I have the differential clock signal entering on an clock input pin in...
View ArticleQuartus 2 13.0sp1 Hardware debugging issue
Hello, I have started using the DE0 board, normally i write my code in C then debug it as hardware on the DE0 for certain Universitie projects, the issue that I'm facing is that on one of my PCs the...
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