Snake game using FPGA in VHDL
Im coding a snake game in VHDL using the DE2-115 FPGA from Altera. I have connected the FPGA with a monitor using VGA protocol to show the game. I have a problem to show the snake and to move it around...
View ArticleClik here to view.
Tutorial: Creating a Nios II Project on DE0-Nano and Quartus II 14.1
Hi Everybody! I'm trying to get my DE0-Nano board work. I'm using the Terasic DE0-Nano user manual and Quartus II 14.1. Using Quartus 11.1sp2, the tutorial in the manual works. I'm getting confused...
View ArticleHTTP Error 404
Hi,, We are working on a project using the available "webserver" demo program in DE2-115 kit manual. we have created our own webpage and tried to fuse in the same way as the one available with demo...
View ArticleCyclone IV and M25P16 8 pins SPI Flash
Hello, I have a board with M25P16 8 pins SPI Flash on it. Now I want to program it with .jic in Active serial mode, for that I instantiated Altera Serial Flash Loader IP according to an370.pdf but I'm...
View ArticleTerasic DE2: Lot of jitter with default SOF, SRAM timing problems, related?
I don't know if anyone could help me with the following issue: when I load up the default SOF (blue background, ALTERA-logo etc) to my DE2 board, I have a _huge_ amount of jitter on the screen. I mean,...
View ArticleCyclone V IO Drive Power Maximum Capacitive Load
Dear community, What is the maximum capacitive load that a Cyclone V IO can drive? I know the IOs have a capacitance of 6 pF when used as input, but I couldn't find information about the maximum...
View Articleterasic Cycone V GX Starter Kit + serdes on HSMC
Hi, I'm trying to implement 3 channel 7:1 serializer with LVDS output on HSMC connector. I've used ALTLVDS_TX to create the module. Design synthesizes fine until I constrain output signals to block 7A...
View ArticleClik here to view.
Simple Signed Adder is complex to understand
Hi guys, still asking beginner questions, sorry. I have this code and cant figure out what the '0' in ('0' & cin) is doing. This is what I think: Lets say we we need to do add two to negative four:...
View Articleissue TErsic-C5G Control Panel V1.0.1
Hi all is the first time I post a question and the story is like this... I just receive my Cyclone V GX Starter Kitand I have downloaded the software for it...
View ArticleNiosII booting from on-chip memory
I am trying to boot a NiosII (HAL only, no other bigger OS) on a Cyclone IV directly from the on-chip memory. I have initialized the memory .hex file and included it in my project. I then recompiled...
View ArticleDDR3 memory testing
Hi, I am new to nios ii tool. I am going to test DDR3 memory. Can anybody tell me how to write source code or can you please provide link to download source code. Thanks in Advance.
View ArticleArrow SoCKit, what interrupt vector accelerometer uses?
I am trying to add support for onboard accelerometer in Linux on Arrow SoCKit board (it uses 5CSXFC6DF31 FPGA chip). I have added ADXL345 chip to my device tree and enabled it in my Linux kernel...
View ArticleCan't use Signal Tap II in Web Edition
I am running the web edition of Quartus II 13.0sp1 on Ubuntu and trying to use Signal Tap II logic analyzer. I keep getting the following error whenever I try to compile: Code: Error (265013): Can't...
View ArticleTSE in SGMII Mode with external FIFO and PLL for PCS Ref Clock
Hi everybody, I try to use the Altera TSE in SGMII Mode with external FIFO. My board is a SoCKit. I need a 125 MHz signal for the pcs_ref_clk and want to keep it simple and do not change the SI5338...
View ArticleClik here to view.
creating a profile in simulink to suport a cyclone III
so i am using Matlab Simulink to program a cyclone III. the model number of the cyclone III is EP3C10E144C8N. i am using the HDL workflow adviser. i chose the FPGA-In-the-Loop option in the target...
View ArticleClik here to view.
Propagation Delay for SPI bus routed through MAX II CPLD
Hello All, I have a question regarding routing an SPI bus through a MAX II CPLD. I am using the set_max_delay to constrain the pin to pin delay on the SPI lines (MISO,MOSI,CLK,CSN), but I have been...
View ArticleDSE II fails with gataddrinfo error
I'm trying to use DSE II (Bundled with Quartus II 14.1 web edition) to do a seed sweep. It fails with this error: Error: [Errno 11004] getaddrinfo failed Has anyone else encountered this?
View ArticleClik here to view.
How to transfer doubles from the nios 2 to FPGA using the avalon interface?
Hi everyone, First a little backstory on this problem I'm encoutering. I have a Altera DE2 board on wich I want to implement my current project. In this project I need to transfer multiple 64 bit...
View ArticleMove data fast inside memory
Hi. I'm wonderng if any could expain for me how to solve my Project. I'm an old amiga demo coder and would like to test my skills on a de2-115 board. I have looked at the UP ip library. The missing...
View ArticleCan't launch quartus.exe: 0xc00007b error
Help please: I try to install Quartus 14.1 web edition on a Windows 7 x64. However, I got this error when try to launch the quartus: quartus.exe: The Application was unable to start correctly...
View Article