Hi everybody,
I try to use the Altera TSE in SGMII Mode with external FIFO. My board is a SoCKit. I need a 125 MHz signal for the pcs_ref_clk and want to keep it simple and do not change the SI5338 clock generator.
If I connect the hsmc_ref_clk directly to the pcs_ref_clk from the TSE everything is compiling but for sure it is the wrong frequency because hsmc_ref_clk has a frequency of 100MHz.
If I place a PLL and feed it with the hsmc_ref_clk and set the output to 125 MHz, I get some error messages at the fitter step when compiling. You can see the error messages below.
Anyone have a suggestion what can I do to get the right frequency?
I try to use the Altera TSE in SGMII Mode with external FIFO. My board is a SoCKit. I need a 125 MHz signal for the pcs_ref_clk and want to keep it simple and do not change the SI5338 clock generator.
If I connect the hsmc_ref_clk directly to the pcs_ref_clk from the TSE everything is compiling but for sure it is the wrong frequency because hsmc_ref_clk has a frequency of 100MHz.
If I place a PLL and feed it with the hsmc_ref_clk and set the output to 125 MHz, I get some error messages at the fitter step when compiling. You can see the error messages below.
Anyone have a suggestion what can I do to get the right frequency?
Code:
Error (14996): The Fitter failed to find a legal placement for all periphery components
Info (14987): The following components had the most difficulty being legally placed:
Info (175029): global or regional clock driver pcs_clk:pcs_clk_inst|pcs_clk_0002:pcs_clk_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 (49%)
Info (175029): auto-promoted clock driver soc_system:u0|soc_system_eth_tse_0:eth_tse_0|altera_xcvr_custom:i_custom_phyip_0|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout~CLKENA0 (36%)
Info (175029): auto-promoted clock driver soc_system:u0|soc_system_eth_tse_0:eth_tse_0|altera_xcvr_custom:i_custom_phyip_0|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout~CLKENA0 (15%)
Error (14986): After placing as many components as possible, the following errors remain:
Error (175001): Could not place 1 global or regional clock driver, which is within Altera PLL pcs_clk
Info (14596): Information about the failing component(s):
Info (175028): The global or regional clock driver name(s): pcs_clk:pcs_clk_inst|pcs_clk_0002:pcs_clk_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0
Error (16234): No legal location could be found out of 82 considered location(s). Reasons why each location could not be used are summarized below:
Error (15123): The following global or regional clock driver locations cannot route to all the required clock core fanouts
Info (175027): Destination: Clock core fanout containing node soc_system:u0|soc_system_eth_tse_0:eth_tse_0|altera_eth_tse_pcs_pma_phyip:i_tse_pcs_0|altera_tse_top_1000_base_x_strx_gx:altera_tse_top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_a_fifo_24:U_DSW|altera_tse_sdpm_altsyncram:U_RAM|altsyncram:altsyncram_component|altsyncram_4vl1:auto_generated|ram_block1a0 and 9 other node(s) driven by auto-promoted clock driver soc_system:u0|soc_system_eth_tse_0:eth_tse_0|altera_xcvr_custom:i_custom_phyip_0|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout~CLKENA0 and global or regional clock driver pcs_clk:pcs_clk_inst|pcs_clk_0002:pcs_clk_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0
Info (175029): 44 locations affected
Info (175029): CLKCTRL_R64
Info (175029): CLKCTRL_R65
Info (175029): CLKCTRL_R66
Info (175029): CLKCTRL_R67
Info (175029): CLKCTRL_R68
Info (175029): CLKCTRL_R69
Info (175029): CLKCTRL_R40
Info (175029): CLKCTRL_R41
Info (175029): CLKCTRL_R42
Info (175029): CLKCTRL_R43
Info (175029): CLKCTRL_R44
Info (175029): CLKCTRL_R45
Info (175029): and 32 more locations not displayed
Error (175006): Could not find path between source fractional PLL and the global or regional clock driver
Info (175026): Source: fractional PLL pcs_clk:pcs_clk_inst|pcs_clk_0002:pcs_clk_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
Info (175013): The fractional PLL is constrained to the region (0, 14) to (0, 63) due to related logic
Info (175021): The fractional PLL was placed in location FRACTIONALPLL_X0_Y15_N0
Error (175022): The global or regional clock driver could not be placed in any location to satisfy its connectivity requirements
Info (175029): 8 locations affected
Info (175029): CLKCTRL_G12
Info (175029): CLKCTRL_G13
Info (175029): CLKCTRL_G14. Already placed at this location: auto-promoted clock driver soc_system:u0|soc_system_hps_0:hps_0|soc_system_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0
Info (175013): The auto-promoted clock driver is constrained to the region (42, 35) to (89, 81) due to related logic
Info (175015): The HPS_INTERFACE_CLOCKS_RESETS soc_system:u0|soc_system_hps_0:hps_0|soc_system_hps_0_fpga_interfaces:fpga_interfaces|clocks_resets is constrained to the location HPSINTERFACECLOCKSRESETS_X52_Y78_N111 due to: User Location Constraints (HPSINTERFACECLOCKSRESETS_X52_Y78_N111)
Info (14709): The constrained HPS_INTERFACE_CLOCKS_RESETS drives this auto-promoted clock driver
Info (175029): CLKCTRL_G15. Already placed at this location: auto-promoted clock driver soc_system:u0|soc_system_eth_tse_0:eth_tse_0|altera_xcvr_custom:i_custom_phyip_0|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout~CLKENA0
Info (175029): CLKCTRL_G8
Info (175029): CLKCTRL_G9
Info (175029): CLKCTRL_G10
Info (175029): CLKCTRL_G11
Error (175007): Could not find uncongested path between source PLL output counter and the global or regional clock driver
Info (175026): Source: PLL output counter pcs_clk:pcs_clk_inst|pcs_clk_0002:pcs_clk_inst|altera_pll:altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER
Info (175013): The PLL output counter is constrained to the region (0, 18) to (0, 63) due to related logic
Info (175021): The PLL output counter was placed in location PLLOUTPUTCOUNTER_X0_Y21_N1
Error (175022): The global or regional clock driver could not be placed in any location to satisfy its connectivity requirements
Info (175029): 30 locations affected
Info (175029): CLKCTRL_G0
Info (175029): CLKCTRL_G1
Info (175029): CLKCTRL_G2
Info (175029): CLKCTRL_G3
Info (175029): CLKCTRL_R82
Info (175029): CLKCTRL_R83
Info (175029): CLKCTRL_R84
Info (175029): CLKCTRL_R85
Info (175029): CLKCTRL_R86
Info (175029): CLKCTRL_R87
Info (175029): CLKCTRL_R58
Info (175029): CLKCTRL_R59
Info (175029): and 18 more locations not displayed