Hi,
I'm trying to implement 3 channel 7:1 serializer with LVDS output on HSMC connector. I've used ALTLVDS_TX to create the module.
Design synthesizes fine until I constrain output signals to block 7A (lvds capable pins routed to HSMC connector).
Error message:
Is it possible to use ALTLVDS_TX with HSMC pins?
Can someone provide a code example?
Never mind, I've been using clock supplied to different block...
I'm trying to implement 3 channel 7:1 serializer with LVDS output on HSMC connector. I've used ALTLVDS_TX to create the module.
Design synthesizes fine until I constrain output signals to block 7A (lvds capable pins routed to HSMC connector).
Error message:
Code:
Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 PLL LVDS output(s))
Error (175001): Could not place PLL LVDS output
Info (14596): Information about the failing component:
Info (175028): The PLL LVDS output name: lvdstxextpll:lvds1|altlvds_tx:ALTLVDS_TX_component|lvdstxextpll_lvds_tx:auto_generated|pll_ena~PLL_LVDS_OUTPUT
Info (14597): No legal location could be found for this component out of 2 considered location(s). Reasons why each location could not be used are summarized below:
Error (175006): Could not find path between the PLL LVDS output and destination pin
Info (175027): Destination: pin HSMC_CLKOUT_p[1]
Info (175015): The I/O pad HSMC_CLKOUT_p[1] is constrained to the region (11, 61) to (66, 61) due to: User Location Constraints (IOBANK_7A)
Info (14709): The constrained I/O pad is contained within this pin
Error (175022): The PLL LVDS output could not be placed in any location to satisfy its connectivity requirements
Error (175022): The pin could not be placed in any location to satisfy its connectivity requirements
Info (175029): 2 locations affected
Info (175029): PLLLVDSOUTPUT_X68_Y1_N2
Info (175029): PLLLVDSOUTPUT_X68_Y2_N2Can someone provide a code example?
Never mind, I've been using clock supplied to different block...