Hi guys, still asking beginner questions, sorry. I have this code and cant figure out what the '0' in ('0' & cin) is doing. This is what I think:
Lets say we we need to do add two to negative four:
(2)0010 + (-4)1101 where the answer is (-2)11110 (last bit '1' indicates the negative sign) so,
(a_sig(n-1) & a_sig) 00010
+ (b_sig(n-1) & b_sig) 11101
+ ('0' & cin) 00
ans 11111 (which is incorrect)
What am I getting wrong?![]()
Also is this signed adder actually efficient cause lots of examples suggest loads of other ways to do it and I can't figure out which one to stick to or it depends on the application?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity examples is
generic(n : integer := 4); -- number of input bits
port(a, b: in std_logic_vector(n-1 downto 0);
cin: in std_LOGIC := '0';
sum: out std_LOGIC_VECTOR(n downto 0));
end examples;
architecture add_sub of examples is
signal a_sig, b_sig: signed(n-1 downto 0);
signal sum_sig: signed(n downto 0);
begin
--convert to signed
a_sig <= signed(a);
b_sig <= signed(b);
--add
sum_sig <= (a_sig(n-1) & a_sig) + (b_sig(n-1) & b_sig) + ('0' & cin);
sum <= std_logic_vector(sum_sig);
end add_sub;
Lets say we we need to do add two to negative four:
(2)0010 + (-4)1101 where the answer is (-2)11110 (last bit '1' indicates the negative sign) so,
(a_sig(n-1) & a_sig) 00010
+ (b_sig(n-1) & b_sig) 11101
+ ('0' & cin) 00
ans 11111 (which is incorrect)
What am I getting wrong?

Also is this signed adder actually efficient cause lots of examples suggest loads of other ways to do it and I can't figure out which one to stick to or it depends on the application?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity examples is
generic(n : integer := 4); -- number of input bits
port(a, b: in std_logic_vector(n-1 downto 0);
cin: in std_LOGIC := '0';
sum: out std_LOGIC_VECTOR(n downto 0));
end examples;
architecture add_sub of examples is
signal a_sig, b_sig: signed(n-1 downto 0);
signal sum_sig: signed(n downto 0);
begin
--convert to signed
a_sig <= signed(a);
b_sig <= signed(b);
--add
sum_sig <= (a_sig(n-1) & a_sig) + (b_sig(n-1) & b_sig) + ('0' & cin);
sum <= std_logic_vector(sum_sig);
end add_sub;