Implementing 18-bit lvds serializer in CPLD

Hello,

Maybe this is a beginners question. I do not yet have a lot of experience using CPLDs. They are a bit more limited than FPGAs.

I was wondering if it is feasible to implement an 18-bit LVDS deserializer on a low cost FLASH CPLD. For a projet I need the deserializer and some simple glue logic. It would be perfect if this could be implemented in an all-in-one chip like one out of the MAX family.

However, I am not sure about the clock recovery part. This probably needs a PLL of some sort.
Can this be done in a MAX?

Thanks in advance for any help.

Ronald