Avalon -> Dual Port RAM -> custom hardware interface
Hi All, I am creating a custom memory mapped device and need to create an 8k byte block of dual port RAM with write-only access from NIOS, and read-only access from the custom hardware side. RAM needs...
View ArticleRun an application using NIOS II processor based on freeRTOS
Hello, I'm still a novice in using Quartus II and EDA tools. I have a basic question. Can I run an application program using NIOS II processor based on FreeRTOS (compiling freeRTOS in NIOS II IDE) and...
View ArticleWarning (18029): Output pin [...] cannot be tri-stated
Warning (18029): Output pin "_subnet_pin_68" driven by bidirectional pin "sram_bus[6]" cannot be tri-stated The Quartus help says: CAUSE: The specified output pin is driven by both the specified...
View ArticleCannot create new project on Altera Monitor Program, Please help
Hi, for some reason I cannot create a new project on altera monitor program on windows. The thing is, not even a window pops up when I try to create a project, not even an error message saying I...
View ArticleImplementing 18-bit lvds serializer in CPLD
Hello, Maybe this is a beginners question. I do not yet have a lot of experience using CPLDs. They are a bit more limited than FPGAs. I was wondering if it is feasible to implement an 18-bit LVDS...
View ArticleClik here to view.
Quartus II 12 Web Edition + ModelSim Altera = output pins are always in 'X'...
Hello! I tried to follow few tutorials on the internet on how to use Quartus + Modelsim, but no matter what I do in the end simulation does not work correctly - all output pins are always in 'X' state....
View ArticleJtag error Centos6.3 Quartus 10.1 error code 89
i've installed quartus II 10.1 linux version on Centos6.3 running on virtualBox and as a root i Created the file 51-usbblaster.rules in /etc/udev/rules.d directory. With the following content: #...
View ArticleWhat is Golden-Top?
Hi I'm brand new to cpld and starting with a max v eval board. In the installation folders there is a project called golden-top. I can't find any proper explanation of it any where on the internet or...
View ArticleClik here to view.
Qsys, trying to connect clock and reset to external pins - how!?
I'm trying to connect my clk_in and reset to external pins however I don't see any option that lets me. Qsys happily throws an error about it though.. how do I fix this? Attached Images External...
View ArticleSOPC Design for PCI Compiler
Hi, I am looking for SPOC design for interfacing only PCI Compiler(verilog) to DDR2 memory using 2c35 PCI development kit. Note:- Already i have DDR2 to PCI design but it was using mega function...
View ArticleClik here to view.
Beacon signal for lowest power mode in PHY IP core
HI.. Currently I works with PHY IP core with PCI Express, in that I had problem related to Beacon signal, I have no any idea about Beacon signal used in lowest power mode P2 in PCI Express, I don't...
View ArticleAS Configuration of NiosII hardware & software images
Hi, I have a requirement that I want to program my serial configuration device - EPCS16 with the hardware and software images of the NiosII system that I am building. Upon power-up, I want the FPGA to...
View ArticleHow to constrain my design
Hi, I'm not sure how I should constrain my design and which timequest commands I should use. In my design there are 5 clock domains. The are clock domain crossing from 4 clocks to the 5th. So to...
View Articlepci_t32 core & DMA
Hi ! I want to design a data aquisition system using pci interface.I have planned to use pci_t32 IP core but I have to use DMA propherty.I know master core supplies dma propherty but I am not sure...
View ArticleClik here to view.
TSE TimeQuest problem on DE2-115
hi all, I've faced problem with one tutorial published by Altera " Testing Triple Speed Ethernet on DE2-115" ftp://66.35.227.3/up/pub/Altera_Mate...d_ethernet.pdf After compiling the project with no...
View ArticleSeeking some advice and technical help regarding creation of multicore system
Hello all, I am trying to create a multicore system that I will use for JPEG encoding. I am using a DE2-115 board along with Quartus 12.1, Qsys and associated build tools for Eclipse. I have some...
View ArticleNios Open Source Alternatives?
Hi Guys, Being but a Hobbyist i want to build an independant design that does not require hardware tethering. Now all my training is in Altera and i've have some Altera products; which due to this...
View Articlecan I use the rate match fifo in custom tranceiver in cycloneV when I use...
can I use the rate match fifo in custom tranceiver in cycloneV when I use Fiber channel protocol？ when I use it , I find some byte be deleted in IDLE state. if can not use rate match fifo,how to do?...
View ArticleKernel bug?
Hi, I am using uClinux 3.1 and trying to run on the NEEK, but after nios2-terminal, I got this unhandle message. Unhandled exception #12 in kernel mode r1: c6000cc0 r2:00000000 r3: 00000b1c r4:...
View ArticleWhy Clk Oscillator waveform is not square in the oscilloscope?
If some body knows please help me regarding these two below questions. 1- Why board's Clock waveform is not square in the oscilloscope? As I am new I use this simple code: architecture behavior of clk...
View Article