Hello! The Board of the company HiTechGlobal S5-PCIE pins RREF
transceiver banks FPGA Stratix V GX are connected to the GND through resistors 2 kom.
In the recommendation of the Altera written that these pins should be connected
through a resistor 1.8 kom. Can the violation of the recommendations
lead to the malfunction of transceiver banks?
transceiver banks FPGA Stratix V GX are connected to the GND through resistors 2 kom.
In the recommendation of the Altera written that these pins should be connected
through a resistor 1.8 kom. Can the violation of the recommendations
lead to the malfunction of transceiver banks?