Struggling to program Spansion Flash memory with .jic file, Cyclone II
Hey all, I've been trying recently to program my project onto flash memory with no success so far. I was hoping someone here might be able to shed some light on the issue. Details: Dev kit: RedCore...
View ArticleAltera 10G on Board S5-PCIE and INTEL X520
Hello! I compiled the project SVGX_ETH_10GBASER_DEMO_DESIGN.qar for the Board HiTechGlobal S5-PCIE with the account of any other connection pins of the FPGA. As the test runs from the system console...
View ArticleSystem Console to inject commands into fifo
Hi, could anyone please outline the steps necessary to allow me to write commands into a fifo in my design using system console or point me to a relevant tutorial? Thanks,
View Articleaccess environmental variables in _hw.tcl files
Hello all, When I try to print an environmental variables in the Quartus TCL Console (e.g. puts $::env(PATH) ) it works, but whenever I try to access it within a _hw.tcl component script it doesn't and...
View ArticleQsys new component - file path keeps changing
Hello, i am working on my first Qsys project and it is running smooth with all built in components and one custom unit i connected in my .bdf file. However, i was trying to a add the I2C unit from...
View ArticleRref pins stratix v gx
Hello! The Board of the company HiTechGlobal S5-PCIE pins RREF transceiver banks FPGA Stratix V GX are connected to the GND through resistors 2 kom. In the recommendation of the Altera written that...
View Articlesimplest way to make a pin high or low in verilog
someone kindly suggest a simplest way to make a pin high or low in verilog the board i am using is DE2 115 thank you
View ArticleHow to look for 3-letter words?
How to look for 3-letter words in the Altera Forum? For example search for I2C, SDI results in: Sorry - no matches. Please try some different terms. :(
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Interrupt Not Enable
Dear Friends, I am trying to use interrupt on Altera DE2_115 board. but it is not working. i am taking LOAD pulse as an interrupt and at every interrupt taking data from external bus "DATA[7..0]" ,...
View Articleelf size too large for hello world application
Hi All, i am new to Altera's Nios-II, so as usual started with hello world template i am able to build it but the elf size is comes about 677274 bytes after applying all the optimizations (according to...
View ArticleFlash Access Problem with dual-NIOS2 config.
Hi, I'm working based on the "web_server" hardware configuration and trying to add on another core. Because of the hardware resources restriction I cliped off ssram controller(ssram) and reduced the...
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Triple Speed Ethernet: MAC Address Insertion
Hi, I'm working on a project which needs a communication between Cyclone III and PC through the Ethernet connection. In this TSE MegaCore user guide, page 4-4, section "Address Insertion", it is said...
View ArticleA question about rd_usedw and wr_usedw for a DCFIFO
Hello all, Recently I used a dcfifo mega core to buffer datas, I found there're 2 signals for usedwidth : rd_usedw and wr_usedw I don't understand the difference between these two signals. Why we need...
View ArticleError Message Click on a Search Result
Hi, I'm new to the forum. I received the following message whenever i clicked on a result after a search is performed. Could one help me resolves this problem. "You don't have permission to access...
View Articleinit binary format
After a lot of hassle I have my SD card up and running. uClinux boots and mounts the filesystem from the SD card. As seen below I've inserted some code into init/main.c to be able to fetch return...
View ArticleArriaII transceiver oversampling
Hi folks, I've been looking everywhere but cannot find an answer to this problem. I know I can recover low rate data using oversampling and lock to reference mode (this works fine with a SDI design)....
View ArticleError (10002): Can't open VHDL or Verilog HDL file
I am new to Altera/Quartus, but do have FPGA design experience. I am trying to complete a lab, but when I try to compile my Qsys generated design, I get: Error (10002): Can't open VHDL or Verilog HDL...
View Articlesimulator error "current device family is not supported by simulation "
hello all my simulator under university program is giving me an error current device family is not supported by simulation i've a DE2-115 board with a cyclone IV E fpga chip, and Quartus II 10.1 full...
View ArticleHow to handle the no connection ports in a module?
In some cases, I want to leave some input or output ports of a module no connection. E.g.: ModuleA modulea_1 (.in1(),.in2(), ,.out1(),.out2(), ); However, if I just program as above, to leave them...
View Articlealways@(*) statement
Hi, I've seen always@(*) in a few tutorials but i'm unsure on where this is a valid sensitive list or whether they're refering the * to be any input you want? And whether it should be used, if it is a...
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