Hi folks,
I've been looking everywhere but cannot find an answer to this problem.
I know I can recover low rate data using oversampling and lock to reference mode (this works fine with a SDI design).
But I have a new application that requires me to recreate the clock, but it seems that I cannot get the transceivers to work with lock to data mode and oversampling (I tried 11x which is unreliable and does not lock properly, and also 3x (810Mps) with a 81Mhz clock at 10 bit channel width in basic mode for the tranceiver. I guess I am effectively trying to cheat the transceiver since it does not work with <600Mpbs signals, but since even high speed signals will have periods where they mimic a low speed signal I'm not sure what the limits are here, or how it locks onto signals).
So my question is, can anyone confirm if lock to data mode will not work for oversampling? (when the signal being oversample is <600Mbps)
Thanks in advance
I've been looking everywhere but cannot find an answer to this problem.
I know I can recover low rate data using oversampling and lock to reference mode (this works fine with a SDI design).
But I have a new application that requires me to recreate the clock, but it seems that I cannot get the transceivers to work with lock to data mode and oversampling (I tried 11x which is unreliable and does not lock properly, and also 3x (810Mps) with a 81Mhz clock at 10 bit channel width in basic mode for the tranceiver. I guess I am effectively trying to cheat the transceiver since it does not work with <600Mpbs signals, but since even high speed signals will have periods where they mimic a low speed signal I'm not sure what the limits are here, or how it locks onto signals).
So my question is, can anyone confirm if lock to data mode will not work for oversampling? (when the signal being oversample is <600Mbps)
Thanks in advance