Hello all,
Recently I used a dcfifo mega core to buffer datas,
I found there're 2 signals for usedwidth : rd_usedw and wr_usedw
I don't understand the difference between these two signals.
Why we need two signals to both read and write side?
Do the read and write side share one fifo or do they cut the fifo into two parts,
For example, we have a dcfifo with a depth of 1024 words,
does it mean 512 words for read and 512 words for write?
thx to advance
Recently I used a dcfifo mega core to buffer datas,
I found there're 2 signals for usedwidth : rd_usedw and wr_usedw
I don't understand the difference between these two signals.
Why we need two signals to both read and write side?
Do the read and write side share one fifo or do they cut the fifo into two parts,
For example, we have a dcfifo with a depth of 1024 words,
does it mean 512 words for read and 512 words for write?
thx to advance