Hello,
I have two clock domains in my design 1. variable clock ~64Mhz (driven from external pll)
2. 100mhz stable clock.
Does anybody have an idea how to check clock 64M existent ( without attaching it to a pll) ??
sampling 64M with 100Mhz will creat a metastability.
thanks
I have two clock domains in my design 1. variable clock ~64Mhz (driven from external pll)
2. 100mhz stable clock.
Does anybody have an idea how to check clock 64M existent ( without attaching it to a pll) ??
sampling 64M with 100Mhz will creat a metastability.
thanks