Merged nios2 branch
From my Wiki reading I'm now in the current "nios2" branch where I should be able to work with MMU and non-MMU projects. I've got a lot of old non-mmu projects so I wanted to start there before even...
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Problem with Quartus II (Web edition) RTL simulation with Modelsim (student...
I recently installed both Quartus and Modelsim. The problem is, i'm unable to simulate with modelsim. After relentlessly browsing the web, i figured i need to choose modelsim as my simulator and output...
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Problem simulating a project with Qsys system instantiated
Hi, I want to simulate a simple project with a Qsys system along with some additional codes inside another top level module. I could simulate with just the codes, but the problem started when i tried...
View ArticleTSE MAC TX READY DEASSERTED WHEN A SECOND FPGA TSE MAC Boots Up
Hi, Device Family : Cyclone 4 GX Tool : Quartus version 11.0 Board/Design : Custom Board with 4 FPGAs. FPGA 1 and FPGA2 have TSE MAC instantiated. FPGA 1 and FPGA2 Connected to ethernet ports through...
View ArticleInternal error during compilation
Hello all, I am facing this error during compilation in my design having DDR3 hard ip. Any help will be appreciated. Internal Error: Sub-system: FOCT, File:...
View Articlenios2 gsl linking problem
hello i am using Nios II EDS 11.1 and i want to use gsl for some processing. i had done all of steps for introducing gsl include path to eclipse. gsl is built with nios ii gcc. and i wrote the blew...
View Articleckeck clock existent
Hello, I have two clock domains in my design 1. variable clock ~64Mhz (driven from external pll) 2. 100mhz stable clock. Does anybody have an idea how to check clock 64M existent ( without attaching it...
View ArticleDE115 Lab 1 part 2 Question
can not compile at x <= SW[7:0];, how to fix it? LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Lab1b IS PORT ( x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); y : IN STD_LOGIC_VECTOR(15 DOWNTO 8); s : IN...
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What Altera VIP blocks don't work as advertised?
Quote: Originally Posted by gwall It should only take a couple of days to write and test if you are familiar with VIP and Avalon. Then you wouldn't have to use the Altera one anymore. I have written...
View ArticlePos phy spi-4.2 ip core
Hi i am trying to establish a communication between two Cyclone-IV FPGA based boards with the help of SPI IP core. I am trying at 100 Mbps data rate a0_arxval signal is asserted if a particular data is...
View Articlehow to use another vhdl file's function?
bin2bcd7 is not in the scope and error at H1:bin2bcd7 port map (X"0001" => bin_in, bcd7_out => HEX0); bin2bcd7.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use...
View Articlestratix 3 fpga interface with ethernet
Hello sir, I am designing a hardware board for general purpose in which FPGA has to interface with ethernet . Can u please tell which ethernet has to be taken and on what basis? and also tell about the...
View ArticleDDR2 vs DDR3 Throughput
Hi all, I have to update a board. The old design (Cyclone IV) used DDR2 Altmemphy running at 133MHz over 16 Bits. The new design (Arria V) will use DDR3 Uniphy with the Hard EMIF running at 533 MHz...
View ArticleDE115 Lab 3 part 2 question Clk does not exist in primitive error
1. how to fix Clk does not exist in primitive error 2. when i use NAND(A,B) in DLatch, got error, why can not directly call? Lab 3 Lab3b.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Lab3b IS...
View ArticleDE115 Lab9 Question Can nios system connect and use my own DIY CPU?
DE115 Lab9 Question Can nios system connect and use my own DIY CPU? i mean create assembly or c code for DIY CPU in DE115
View ArticleTransceiver toolkit doesn't recognize a link
Hello, What should be done in the transceiver-oriented design in order to be exploited with "Transceiver Toolkit". I've tried 2 examples downloaded from Altera site: 10Gbps low latency10GBase-R In 1st...
View ArticleDE2 (cyclone2 EP2C35F672C6) can compile successful but cant run on board
I am first time using Quartus II 12.1 free edition. I run just simple coding module part1 (SW, LEDR); input [17:0] SW; output [17:0] LEDR; assign LEDR = SW; endmodule Full Compilation successful with...
View Articleinstalation of altera complete design v10.1 (devices)
i recently try to instal the altera complet design ,but i was in frot of this error "you successfully installed the quartus II software but did not install any device ;if you want install device...
View Articlenios2-terminal and jtag
Hello all, I am running Nios2 on Ubuntu 12LTS and I have received the following error when trying to run nios2-terminal: $ sudo bash ./nios2-terminal ./nios2-terminal-wrapped: error while loading...
View ArticleMultiple projects/SOFs to one RBF
I have two projects, factory and application. Upon compiling each project, I have two .sof files, factory and application. I am able to convert both .sof files into one .jic. However, I'd like to...
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