how to use another vhdl file's function?

bin2bcd7 is not in the scope

and

error at H1:bin2bcd7 port map (X"0001" => bin_in, bcd7_out => HEX0);

bin2bcd7.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bin2bcd7 is
Port ( bin_in : in STD_LOGIC_VECTOR (3 downto 0);
bcd7_out : out STD_LOGIC_VECTOR (6 downto 0));
end bin2bcd7;

architecture Behavioral of bin2bcd7 is
...

top file - Lab2.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Lab2 is
Port (
HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
end Lab2;

architecture Behavioral of Lab2 is
begin
bin2bcd7(X"0001",HEX0);
end Behavioral;

or

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Lab2 is
Port (
HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
end Lab2;

architecture Behavioral of Lab2 is
component bin2bcd7
port (bin_in : in STD_LOGIC;
bcd7_out : out STD_LOGIC
);
end component;

begin
H1:bin2bcd7 port map (X"0001" => bin_in, bcd7_out => HEX0);
end Behavioral;