What I want to do, is to write an SPI Master that drives both the SCLK (ouput) and MOSI (output) from the FSM and also samples MISO (input) in the FSM.
E.g. I clock the FSM process with a 50 MHz clock and generate a 25 MHz SCLK, by toggling SCLK every FSM clock.
I would drive MOSI at each rising edge of SCLK and sample MISO at each falling edge of SCLK.
The slave interface requires that.
My question is, how do I need to constrain the outputs that there is now phase shift between the outputs (SCLK and MOSI).
Or can I rely on them "leaving" the FPGA synchronously, since the come out of the same clocked process.
All examples for source synchronous interfaces I have seen have the clock coming out of a PLL and not out of an FSM.
Or is this not a good approach?
E.g. I clock the FSM process with a 50 MHz clock and generate a 25 MHz SCLK, by toggling SCLK every FSM clock.
I would drive MOSI at each rising edge of SCLK and sample MISO at each falling edge of SCLK.
The slave interface requires that.
My question is, how do I need to constrain the outputs that there is now phase shift between the outputs (SCLK and MOSI).
Or can I rely on them "leaving" the FPGA synchronously, since the come out of the same clocked process.
All examples for source synchronous interfaces I have seen have the clock coming out of a PLL and not out of an FSM.
Or is this not a good approach?
