Global way to set NUM_PARALLEL_PROCESSORS 1 for all Quartus jobs?
I am trying to automate test flows with Quartus in UGE (Univa Grid Engine; formerly SGE) and machines in my farm are running into load problems because Quartus tries to set the default number of...
View ArticleTiming Constraints for Source Sync Interface with clock coming out of FSM...
What I want to do, is to write an SPI Master that drives both the SCLK (ouput) and MOSI (output) from the FSM and also samples MISO (input) in the FSM. E.g. I clock the FSM process with a 50 MHz clock...
View ArticleMAX II Development Board Kit - Incorrect pinout
Hi! I noticed the pinout provided for the expansion header pins in Figure 3 from document MAX II Development Board Reference Manual (Document version 6.0.1 October 2006) shows that Pin 2 from connector...
View ArticleBoot Linux from SPI flash on De0-nano
For a project I am required to boot Linux from SPI flash onto my De0-nano board. Currently I use the command terminal to program the board with quartus commands and telnet to load a linux kernel I...
View ArticleGenerating 400MHz external clock (Cyclone V)
Hello, I'm trying to generate a 400MHz clock signal from my Cyclone V in order to drive the clock input for an external ADC, but I'm getting severe attenuation on the clock signal. Details: -I'm using...
View ArticleThe problem of useing EP2C8Q208 to achieve 100ms delay
I use EP2C8Q208 to achieve 100ms delay, and the resource occupancy increased by only 1%, but I find the process can not work correctly. However,when the delay is 4ms, the program is working correctly....
View ArticleGetting Slow Frame Rate using Frame Buffer Driver on Cyclone IV Board
Hi, I am developing Frame Buffer based Video Driver to Play upto 720P Resolution Video on Cyclone IV board in Linux Platform. I have used concept of Linux PCI Driver as well as Virtual Frame Buffer...
View ArticleALtera TSE frame reception
Please help me with altera TSE frame reception. I would like to know that how should I get the exact length of frame received? And like tse_mac_raw_send() is there any api for reception of frames w/o...
View ArticleNios 2 communication without using nios2-terminal
Hello, I have a board with a NIOS 2 processor connected to a Lnux PC through a USB Blaster cable. I know all the commands for the NIOS 2 and I can communicate from the Linux PC using the...
View ArticleEthernet communication between FPGAs
Hi everyone, I'm working on a project where I have two boards (One Master and one Slave), and I need to realise an Ethernet communication between those two. Both the boards uses a Cyclone V FPGA, so I...
View ArticlearriaII GX flash program
By writing JIC file from JTAG connector,I config FPGA. It is follwing route. Jtag connector->FPGA->EPCS serial flash Can I write sof and elf file by flash programmer using the route...
View ArticleRAM Bit errors after the two boot stages SoCKit Part1
Hello, I have a very uncommon problem with Linux on the HPS (Cyclone V) and/or with two previous boot stages. At the moment I dont have any other ideas to solve this other than listed below. I will...
View ArticleSGDMA memory to memory from HPS to FPGA
Hi everybody, this is my current situation: I have realized a custom FPGA component, which exposes two Avalon MM Slave Interfaces (one to write data to it and one to read data from it). Then, I have a...
View ArticleOpen CV 3.0 Altera OpenCL SDK
We are discussing OpenCL for possible use in an upcoming project that will be based upon the Cyclone V platform. OpenCV 3.0 appears (claims) to support OpenCV assuming appropriate drivers are...
View ArticleALTFP_MUL as custom instruction not reseting variable value.
Hello. I´m trying to do a simple float point multiplier for Nios E. My custom instruction is just ALTFP_MUL block with a top level with clk, clk_en, reset, and the two 32bits inputs and one 32bits...
View ArticleReference Clock Input for High-Speed Transceivers in Terasic TR4 Eval Board
I am trying to use the Startix IV FPGA on the TR4 Eval Board from Terasic to receive a 15-bit word at 2.3Gbps. The channels use differential signalling and are source synchronous. Also, I have the...
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Ring oscillator output always high
Hi Folks, I've built three simple ring oscillators (3, 7 and 15 NOT gates), they are connected to 3 standard I/O ports on my board (EP4CE6E22C8) but unfortunately their outputs are all high and never...
View Articlequestions about flash in nios
i have some other questions, 1. can the configure flash can be used as data storage device at the same time? 2. if the answer is yes, how can i know how many space the configure data occupy? 3. if the...
View ArticleVideo Lincence
Hi, I just want to know whether a separate licence is required for SDI, Clocked Video Output and Test Pattern Generator IP cores.:) I can compile the design of Clocked Video output and Test Pattern...
View ArticleBFM AXI4lite
Hi! When I compile BFM with Modelsim, there is a problem: Cannt find mgc_axi4_pkg. Someone knows what can I do? thx
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