RAM Bit errors after the two boot stages SoCKit Part1

Hello,
I have a very uncommon problem with Linux on the HPS (Cyclone V) and/or with two previous boot stages. At the moment I don’t have any other ideas to solve this other than listed below. I will briefly describe by problem.

Aim:
The aim is to boot the HPS with Linux from non standard devices (no NAND, QSPI,.. devices) where the FPGA is configured first and the preloader resides within the FPGA image. I’m using the SoCKit. At the moment the R/W access is done by a JTAG connection which transfers the data (U-Boot, DTB, uImage) into the RAM.

Parameters: Quartus 14.1 with the included U-Boot source; Buildroot; Linux Kernel from rocketboards 3.10.37-ltsi socfpga -> up to date

Implementation/bootflow:

1. The preloader sets a bit in RAM (Avalon Bus) to show that the data can be transferred to the SDRAM after he has calibrated the SDRAM (the own code resides at the end of void spl_board_init(void) within spl.c (/arch/arm/cpu/armv7/socfpga/spl.c) -> function polls for another bit whether the data was transferred or not (handshaking)
2. JTAG transfers the data and sets the according bit
3. Preloader calls U-Boot
4. U-Boot jumps to uImage

Result:

• Preloader runs successfully ; RAM calibration passed, scrubbed memory section
• Data is transferred successfully via JTAG
• U-Boot starts and is jumping the kernel successfully -> Linux is booting