Using AXI on Stratix FPGA

Hi,

I want to use a AXI master and slave in design. How do I use the AXI ip core provided in quartus? I dont want to create a completely new design, that is why creating a new design (and including the AXI ip) using Qsys is not an option.
There are a lot of signals for AXI, such as
axs_awid,
axs_awaddr,
axs_awlen,
axs_awsize,
axs_awburst,
axs_awlock,
axs_awcache,
axs_awprot,
axs_awvalid,
axs_awready,

axs_wid,
axs_wdata,
axs_wstrb,
axs_wlast,
axs_wvalid,
axs_wready,
and so-on.

1. How are the signals differentiaed between the master and slave? For example, in Xilinx we have, M_AXI_arready (for master) and S_AXI_arready (for slave)

2. A general question, in the .v file, I have something like
system system_i
(
.......
.......
.M_AXI_araddr(M_AXI_araddr),
.M_AXI_arburst(M_AXI_arburst), // burst type
.M_AXI_arcache(),
.M_AXI_arid(M_AXI_arid),
.M_AXI_arlen(M_AXI_arlen),
.......
.......
);

So how is the AXI interface added into this design? Using this interface?

Thanks