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divide by two operation in vhdl

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Hai,

I have write vhdl code for divide by two operation. Below is the short code:
Code:

SRL16_a:process(CLK)  begin                        --  SRL16
        if CLK'event and CLK='1' then
            if en='1' and (cycle=0 or cycle=2 or cycle=4 or cycle=6) then   
                sr16<=di & sr16(0 to 14);                  -- shift SRL16         
            end if;
        end if;
    end process;   
    a1<= sr16(ad1);                -- output from SRL16
SM_B:process(clk,rst)
    begin
        if RST = '1' then     
            di <= (others => '0');         
            bp <= (others => '0');     
            bm <= (others => '0');
        elsif CLK = '1' and CLK'event then     
            if en = '1' then                       
                if    d_signed =0 then
                    di<=unsigned(DATA_IN) - unsigned( a1_2);
                else
                    di<= DATA_IN;
                end if;   
                add_temp<=SXT(di,9)+a1;
                bp<='0'& add_temp(8 downto 1);
                bm<=SXT(di,9)-a1;
               
            end if;
        end if;
    end process;

I try to add to numbers (di & a1), and then divide the sum by 2. When I simulate the testbench code in ModelSim, the values of add_temp and bm is correct. But, the values of bp is wrong (not as manual calculation). I attach the figure. Anyone please help me. Do I make anything wrong?Thank in advance
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