change object mode to buffer error about TFlipFlop
i see Verilog can DT <= QQ ^ TT; but in vhdl is not the case. How to translate Verilog above to VHDL LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY TFF3 IS PORT ( TT, CC : IN STD_LOGIC; QQ : OUT...
View ArticleWhat is the difference between 3 types of DMA: Chaining DMA, SGDMA, mSGDMA?
What is the difference between 3 types of DMA? 1). Chaining DMA described in AN456 ( PCI Express High Performance Reference Design ) 2). SGDMA described in Embedded Peripherals IP 3). Modular SGDMA (...
View ArticleDE2 board- best suitable method for storing large scale of output data
I'm working with millions of data and I need to store my output in a proper storage. Which can be the best suitable method in DE2 board? (SDRAM-8MB, Flash-4MB) Further I need more details on doing it....
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problem using ModelSim-Altera 10.1b (Quartus II 12.1) Starter Edition for...
First, I apologize for my poor English, I'm trying to improving it. In short, I've just installed ModelSim-Altera 10.1b (Quartus II 12.1) Starter Edition and Quartus II 12.1 Web Edition (32-Bit)...
View ArticleModelSim - Design unit not found
I'm trying to use ModelSim to simulate a Verilog design that requires the megafunction lpm_mult. I have found entries for lpm_mult in the 220model.ver and the lpm.ver libraries. In the Start Simulation...
View ArticleUnique MAC address without using a flash memory and without prompting the user?
Dear Sirs, I am facing a little challenge with MAC addresses here. The default way of assigning a MAC address is by reading it from flash memory. Below is an example (from Code:...
View Articlelaunch Modelsim 10.1 in linux
Hi, I just installed the Modelsim 10.1 on ubuntu(12.10) but I don't what should I do to start the program! Thanks
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divide by two operation in vhdl
Hai, I have write vhdl code for divide by two operation. Below is the short code: Code: SRL16_a:process(CLK) begin -- SRL16 if CLK'event and CLK='1' then if...
View ArticleArria V GX Starter Kit
Is Arria V GX Starter Kit (http://www.altera.com/products/devki...v-starter.html) really available? I tried to contact Altera sales but they said they don't have this board in their database? The same...
View Articlecompare EP3C80F780C8N and EP3C5E144C8N
Hi all, I am a beginner of using Altera. Currently, I am doing a project which optimizes the cost of a device by replacing EP3C80F780C8N with EP3C5E144C8N, while still using the old vhdl code. They are...
View ArticleVitesse PHY Register controlling Via MDIO using Nios Processor
Hiii, Anybody know how Nios II can control VSC8486 Vitesse Phy via MDIO ie how to write and read via MDIO to Vitesse External phy ?? pls share your experience asickrishna
View Articleinterfacing Altera Cyclone 3 FPGA to a peripheral using UART
Hi everybody, i'm working in my 1st project in FPGA Altera Cyclone 3 (EP3C25) and i have to connect a peripheral that have only an UART interface to my FPGA. which interface of the FPGA board i have to...
View Articleunexpected Quartus optimisation
In my project I have some small counters. For example one counter counting up 0,1,2,0,1,2... This counter is under asynchronous reset and the reset signal is presynchronised (say through register R)....
View ArticleCyclone V SOC development kit
Hi Where can i find the bootloader and linux source code for Cyclone V SOC dual-core ARM® Cortex-A9 MPCore processor? Also the toolchain for the cross compilation for bootloader and linux for the...
View ArticleDDR2 Memory Controller on Cyclone IV: Pin placement error with VREF
Hello Everybody, I'm working on a CycloneIV design with an DDR2 SDRAM controller. To find the correct pin placement for the PCB design, I'm verifying it with a stripped down project that so far only...
View ArticleNewbie Q: Running Quartus 2 offline
I am using Quartus II 11.1 floating license on a Windows 7 64-bit laptop. How can I work offline? Do I have to be able to access the license server only when I start Quartus, or constantly, or when...
View ArticleNios Bootup
Nios II cannot boot up 1. reset -> CFI flash 2. exception -> SDRAM 3. Linker setting: .bss .heap .rodata .rwdata .stack .txt => SDRAM pls find the attachment ,this some tool setting pls help...
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Linker Error
Nios II cannot boot up 1. reset -> CFI flash 2. exception -> SDRAM 3. Linker setting: .bss .heap .rodata .rwdata .stack .txt => SDRAM pls find the attachment ,this some tool setting pls help...
View ArticleCustom Flash is not supported in Altera Qsys 12.0
Custom Flash is not supported in Altera Qsys 12.0, please let us know immediately, how to resolve this. we are using startix V FPGA
View ArticleXAUI and 10GbE MAC Configuration
Please share the Register details (ie what are all the registers Nios want to configure) XAUI and 10GbE MAC Configuration
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