Hello Everybody,
I'm working on a CycloneIV design with an DDR2 SDRAM controller. To find the correct pin placement for the PCB design, I'm verifying it with a stripped down project that so far only instantiates the top level of the megafunctions output.
I was running the tcl script "*_pin_assignments.tcl" and placed the pins after reading a lot in the Cyclone IV documentation (DQS- and DQ groups, diff-pair for the clk).
So I got now to a point where Analysis&Synthesis runs fine, but in the Fitter I'm stuck with some error messages that I don't understand:
Or could there be some problem with Quartus II if not all the pins in a bank are used? For sure they are all at a standard with 1.8V VCCIO.
I hope someone can give me a hint on how to interpret this error. I read several ressources on the memory-IF design with Quartus II / Cyclone IV but cannot see how to continue.
Thanks,
Cheers,
Simon
I'm working on a CycloneIV design with an DDR2 SDRAM controller. To find the correct pin placement for the PCB design, I'm verifying it with a stripped down project that so far only instantiates the top level of the megafunctions output.
I was running the tcl script "*_pin_assignments.tcl" and placed the pins after reading a lot in the Cyclone IV documentation (DQS- and DQ groups, diff-pair for the clk).
So I got now to a point where Analysis&Synthesis runs fine, but in the Fitter I'm stuck with some error messages that I don't understand:
Error: Cannot place I/O pin mem1_clk[0] in pin location AA17 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available
Error: Cannot place I/O pin mem1_clk_n[0] in pin location AB17 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available
Error: Cannot place I/O pin mem1_dqs[0] in pin location AB9 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available
Error: Cannot place I/O pin mem1_dqs[1] in pin location V10 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available
Error: Cannot place I/O pin mem1_dq[0] in pin location AA9 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available
(...and so on for all DQ[0..15])
I thought that the "SSTL-18 Class I" does not require a VREF voltage. Or is it necessary to define something more than the VCCIO at 1.8V for the bank?Error: Cannot place I/O pin mem1_clk_n[0] in pin location AB17 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available
Error: Cannot place I/O pin mem1_dqs[0] in pin location AB9 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available
Error: Cannot place I/O pin mem1_dqs[1] in pin location V10 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available
Error: Cannot place I/O pin mem1_dq[0] in pin location AA9 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available
(...and so on for all DQ[0..15])
Or could there be some problem with Quartus II if not all the pins in a bank are used? For sure they are all at a standard with 1.8V VCCIO.
I hope someone can give me a hint on how to interpret this error. I read several ressources on the memory-IF design with Quartus II / Cyclone IV but cannot see how to continue.
Thanks,
Cheers,
Simon