unexpected Quartus optimisation

In my project I have some small counters. For example one counter counting up 0,1,2,0,1,2...
This counter is under asynchronous reset and the reset signal is presynchronised (say through register R).
The counter output is used as select input to a wide registered mux (say register M) which itself is not under reset.
After some compilations quartus says the path from register R to register M violates setup. But I have not put any reset on the mux register.
I know it could be some sort of optimisation possibly register retiming but why not respect my reset plan. Applying reset to this wide mux
is no good as it does not need it and it is quite wide putting too much work on timing closure.

Any idea why quartus doing that and how to stop it.

Thanks

P.King