Use VHDL to design a model of a three port register file. The register fileis composed of eight 8-bit registers. The register file has two 8-bit outputs(ports A and B ) and a single 8-bit input (port C). Each port has an associated3-bit address input for selecting one of 8 registers for output (A and B ports)or input (C port). Port C has an associated Clk signal for transferring theinput on port C to the addressed register on the falling edge of the Clksignal. Your model should beparameterized to allow the number and bit-width of the register file to bescaled using generic parameters.
I'm having trouble doing this assignment. I was wondering if there was anyone that could help. I know I'm supposed to assign the values A,B,C to A_adr, B_adr, and C_adr, respectively.
I'm having trouble doing this assignment. I was wondering if there was anyone that could help. I know I'm supposed to assign the values A,B,C to A_adr, B_adr, and C_adr, respectively.
Code:
library ieee;
use ieee.std_logic_1164.all;
entity regfile is
generic ( dw : natural := 8;
size : natural := 8;
adrw : natural := 3);
port ( A : out std_logic_vector(dw-1 downto 0);
B : out std_logic_vector(dw-1 downto 0);
C : in std_logic_vector(dw-1 downto 0);
A_adr : in std_logic_vector(adrw downto 0);
B_adr : in std_logic_vector(adrw downto 0);
C_adr : in std_logic_vector(adrw downto 0);
W_Clk : in std_logic);
end entity regfile;