Does Triple-Speed Ethernet IP Core support IPV6?
Does the Triple-Speed Ethernet IP Core support IPV6? If not is there a core available that supports IPV6? Thanks.
View ArticleQuartus, compile project, fitter, internal error
Hello, I get this error when compiling standard configuration - stage Fitter (Place&Route) Code: Internal Error: Sub-system: VPR20KMAIN, File:...
View Articlehow to solve ModelSim exit Code 9 problem
hello, i am writing a 1024 point FFT code in system verilog using Modelsim Altera starter edition. the compilation of the code was a success but when i try to simulate the test code, all the modules...
View ArticleDe0-nano jtag I/O standard
Hi everybody I was doing a simple nios2 tutorial whit my de0-nano board while I noticed one thing. After synthesis I can find, in the pin planner, the reserved pins for the JTAG interface and the I/O...
View ArticleClock Assignment on (X,Y) region for DDR3 SDRAM Controller with UniPHY IP in...
Can anyone please help explain how does the tool go about the (x,y) coordinate of region to decide which fractional PLL the clock will use to output clock to logic? I am targeting Arria V GX 896-pin...
View ArticleThree Port Register File
Use VHDL to design a model of a three port register file. The register fileis composed of eight 8-bit registers. The register file has two 8-bit outputs(ports A and B ) and a single 8-bit input (port...
View Articlerx_clkout - route to which output pin
I'm planning to use the ALT_GX module in an Arria II GX FPGA like indicated here: http://www.altera.com/literature/an/an610.pdf Page 7, figure 4. The question I have is which output pin should I route...
View ArticleQSys/NIOS triple RS232 port
Gentlemen, I have a DE2-70 board with a std RS232 port. I was wondering if I could modify the example Media Computer using QSys to add 2 additional RS-232 ports using the expansion connector at 3.3V...
View ArticleIssue when deleting SOPC components in Terasic's demo projects
Hello all, I am using Quartus II V.10.1 with a DE2 board. I'm trying to modify DE2_SD_Card_Audio from Terasic's V.1.6 demo CD. Specifically, there is an error with the USB component (ISP1362) that is...
View ArticlePCB design for Cyclone III 144 pins
Hi all, I am about to design a brand new PCB board for a cyclone III 144 pins using Eagle Cadsoft. In the software, I can find a package for EQFP144. Sadly, I am totally clueless about what to do next...
View ArticleThe expected CPU name does not match the selected target CPU name
I'm using altera quartus II subscription edition and when I connect to nios cpu through target connections it doesn't show the correct cpu name. Instead it automatically gets some other cpu name and...
View ArticleData rates for Cyclone IV I/O Standards
Hi there, I am looking for data rates (speed in Mbps) for all Cyclone IV I/O standards. To be specific datarates relative to each independent I/O standards. Does Altera characterize this data ? If yes,...
View Articlezero all elements in an array
Hello, I created a 4x4 array which I want to zero in a one easy step; not as a default value in declaration/initialization, but in the program when a certain condition is met. TYPE arr IS ARRAY(3...
View ArticleDe2 ic tester design
Hi, I am working on a project to design an IC tester using Altera DE2, i am curious whether the DE2 have the features to act as a PMU (precision measurements units) or required external hardware...
View Articleerror with using a macro
Hello, Example with a_74283. LIBRARY altera; USE altera.maxplus2.all; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY macro_eg IS PORT ( num_a :IN STD_LOGIC_VECTOR (4 DOWNTO 1); num_b :IN...
View ArticleHow nios can read and write External FPGAs
Hi, In my project am using 4 FPGAs 1) First FPGA am using Nios II 2) I want to access/ Control Other FPGA registers so i have created a custom protocol in slave and master side ir Nios side am planing...
View ArticleModelSim/QuestaSim Batch mode with waveform stimulus
Hi , I have been trying to simulate a very large setup on ALTERA Modelsim 6.6 and the simulation time of 5ms in real time is taking almost 18 hours. And performing debug at this rate is really...
View ArticleHow do I get the address of the PHY port on an EP3C120 dev board?
Hello, I'm working with the Cyclone III dev board (EP3C120), where I can use the Triple Speed Ethernet MegaCore for a communication. But for this I need to have the address of the PHY port on the...
View Articleproblem with a multiprocessor design in Qsys
Hi all, I want to test a multiprocessor design with Quartus 11.1 and qsys I generated a system containing 2 NIOSII each processor is connected to its on-chip memory and its jtag uart the two processors...
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