Avalon bridge accross fpgas using Dual Clock FIFOs and Alt-LVDS

Hi,

I need a little advice/direction regarding connecting two fpgas via a bus.

HW setup

Stratix III (DE3) Stratix V
8 x LVDS Tx pairs ---------------------> 8 x LVDS Rx pairs

Any other I/O requirement for signaling is flexible. But for data, the DE3->Stratix V is limited at these 8 LVDS pairs.

The bus has to be capable of running at around 10g in total. i.e. around 1.2-1.4Gbps per LVDS pair.
Data is mainly from the DE3 to the Stratix V.

Ideally I would like to have seamless Avalon interfaces on both sides.

Can a dual-clock Avalon ST Fifo span across to the other FPGA via the AltLVDS megafunction?

e.g.

On the Stratix III (DE3)
I configure the Dual Clock Fifo
I use the SGDMA(scatter gather) to take data and Stream it out to a Dual Clock Fifo using Avalon ST.
I export the signals of the output side of the Dual Clock Fifo.
I connect the signals to the alt-lvds Tx megafunction.
The valid signal of the FIFO will act as the LVDS Clock for the transfer.

On the Stratix V side.
I receive the data via the alt-lvds Rx megafunction.
I put it in another Dual Clock FIFO and another SGDMA to read the data.

Can all this achieve around 10G..

Comments and suggestions (or complete alternate methods) welcome.

Regards
Zubair